Shin-ichi O'uchi

Variability Analysis of TiN Metal-Gate FinFETs

Variability of TiN FinFET performance is comprehensively studied. It is found that the variation of the in the FinFET occurs and the standard deviations of the of nMOS and pMOS FinFETs are almost the same. From the analytical results, it is found that the variation of the TiN FinFET is due to the work function variation (WFV) of TiN metal gate. The WFV is also responsible for the on-current variation.

Cointegration of High-Performance Tied-Gate Three-Terminal FinFETs and Variable Threshold-Voltage Independent-Gate Four-Terminal FinFETs With Asymmetric Gate-Oxide Thicknesses

Cointegration of titanium nitride (TiN)-gate high-performance tied-gate three-terminal FinFETs with symmetric gate-oxide thicknesses (tox1=tox2=1.7 nm) and variable threshold-voltage Vth independent-gate four-terminal (4T) FinFETs with asymmetric gate-oxide thicknesses (tox1=1.7 nm for the driving-gate-oxide, and tox2=3.4 or 7.0 nm for the control-gate-oxide) has been successfully developed using conventional reactive sputtering, two-step Si-fin and gate-oxide formation, and resist etch-back processes. A significantly improved subthreshold slope and an extremely low OFF-state current Ioff are experimentally confirmed in the asymmetric gate-oxide thickness 4T FinFETs by increasing the control-gate-oxide thickness to twice or more the driving-gate-oxide thickness. The developed techniques are attractive for high-performance and low-power FinFET very large-scale integration circuits

Enhancing SRAM cell performance by using independent double-gate FinFET

SRAM cells with Vth-controllable independent double-gate (IDG) FinFETs have been successfully fabricated. The performance of the fabricated SRAM cell with various circuit topologies has been investigated comprehensively. Both a reduction of leakage current and an enhancement of read and write noise margins have been successfully demonstrated by introducing the IDG FinFETs into the SRAM cells.

Four-Terminal FinFETs Fabricated Using an Etch-Back Gate Separation

A novel resist etch-back process for fabrication of separated-gate four-terminal FinFETs has been investigates. This process enabled co-fabrication of three-terminal (3T) and four-terminal (4T) FinFETs on a same chip. The fabricated 3T-FinFET shows excellent sub-threshold characteristics and drain induced barrier lowering (DIBL) value whereas the 4T-FinFET provides efficient Vth controllability. The effective Vth controllability with keeping a small sub-threshold slope has been confirmed in the synchronized double gate (DD) operation mode

Independent-Double-Gate FinFET SRAM for Leakage Current Reduction

An independent-double-gate (IDG) fin-type MOSFET (FinFET) SRAM has been successfully fabricated with considerable leakage current reduction. The new SRAM consists of IDG-FinFETs which have flexible V th controllability. The IDG-FinFET with a TiN metal gate is fabricated by a newly developed gate-separation etching process. By appropriately controlling the V th of the IDG-FinFET, we have successfully demonstrated the reduction of the leakage current and power consumption of the SRAM circuitry.

Decomposition of On-Current Variability of nMOS FinFETs for Prediction Beyond 20 nm

ON-current (I_on) variability is comprehensively investigated for fin-shaped FETs (FinFETs) by measurement-based analysis. Variation sources of I_on are successfully extracted as independent contributions of threshold voltage V_t, transconductance G_m, and parasitic resistance R_para. As well as V_t variability, G_m variation exhibits a linear relationship in the Pelgrom plot. However, the G_m variation is not reduced with scaling the gate dielectric thickness unlike the V_t variation. Perspective for 14-nm FinFETs represents that the G_m variation will be the dominant I_on variation source. A solution to reduce the G_m variation for the FinFET is also proposed.

Nanoscale Wet Etching of Physical-Vapor-Deposited Titanium Nitride and Its Application to Sub-30-nm-Gate-Length Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor Fabrication

The nanoscale wet etching of physical-vapor-deposited (PVD) titanium nitride (TiN) and its application to sub-30-nm-gate-length fin-type double-gate metal–oxide–semiconductor field-effect transistor (FinFET) fabrication are systematically investigated. It is experimentally found that PVD-TiN side-etching depth can be controlled to be one-half of PVD-TiN thickness with precise time control using an ammonium hydroxide (NH4OH) : hydrogen peroxide (H2O2) : deionized water (H2O) = 1 : 2 : 5 solution at 60 °C. Using the developed nanoscale PVD-TiN wet etching technique, sub-30-nm-physical-gate-length FinFETs, 100-nm-tall fin-channel complementary MOS (CMOS) inverters and static random access memory (SRAM) half-cells have successfully been fabricated and demonstrated. These experimental results indicate that the developed nanoscale PVD-TiN wet etching technique is very useful for tall fin-channel CMOS fabrication.

Experimental Study of Effective Carrier Mobility of Multi-Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with (111) Channel Surface Fabricated by Orientation-Dependent Wet Etching

We present an experimental study of effective carrier mobility ( µeff) of multi-fin-type double-gate metal–oxide–semiconductor field-effect transistors (FinFETs) with a (111) channel surface fabricated by orientation-dependent wet etching. The peak values of the obtained µeff of electrons and holes are approximately 300 and 160 cm2/(V s), respectively, which are close to those in (111) bulk metal–oxide–semiconductor field-effect transistors (MOSFETs). Moreover, the effective electric field (Eeff) dependence of the µeff of electrons and holes shows a good agreement with the mobility universal curves of (111) bulk MOSFETs. These results indicate that the quality and channel surface roughness of Si-fins by orientation-dependent wet etching are excellent. The obtained results of µeff are very useful for the modeling and design of FinFET-complementary metal–oxide–semiconductor (CMOS) circuits and the developed wet etching technique is very attractive in the fabrication of ultrathin and high-quality Si-fin channels.

Metal-Gate FinFET Variation Analysis by Measurement and Compact Model

A compact model (CM) for fin-type FETs (FinFETs) was successfully developed and applied to variability analysis of a fabricated state-of-the-art metal-gate (MG) FinFET. By combining the statistical measurements with the CM calibration, V th variation was, for the first time, broken down into structure-based (silicon fin thickness and gate length) and material-based (gate work function) components. As a result, the measured variation of MG FinFET performance was successfully reproduced by the CM. Characterization using the CM with the measured statistical data provides insight on the gate work function variation of 16 meV in short-channel molybdenum (Mo) gate FinFETs.

Tunnel Field-Effect Transistors with Extremely Low Off-Current Using Shadowing Effect in Drain Implantation

Tunneling field-effect transistors (TFETs) were investigated. To realize the potentially low off-current characteristics of the TFETs, the offset drain structure is preferred. We have proposed an oblique drain implantation process utilizing the shadowing effect to fabricate the offset drain, and the effectiveness was studied by simulation and experiment. Extremely low off-currents of 40 fA/µm for the P-TFET and 15 fA/µm for the N-TFET have been demonstrated experimentally.