Hiromi Yamauchi

Demonstration, analysis, and device design considerations for independent DG MOSFETs

This paper describes a comprehensive study on the threshold voltage (V/sub th/) controllability of four-terminal-driven double-gate (DG) MOSFETs (4T-XMOSFETs) with independently switched DGs. Two types of 4T-XMOSFETs (fin and vertical) are experimentally demonstrated and their V/sub th/ controllability is thoroughly investigated in relation to the initial V/sub th/ in the DG-mode based on comprehensible modeling of the devices. Based on the investigation and simulated predictions, device design guidelines for 4T-XMOSFETs are proposed. Decreasing the workfunction of the DGs and increasing the oxide thickness of the second gate (T/sub ox2/) are preferable for improving the performance of the 4T-XMOSFET. The optimum workfunction of DGs for attaining low I/sub off(stand-by)/ and high I/sub on(active)/ under the limited V/sub g2/ condition is also proposed.

A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel

Highly threshold voltage (V/sub th/)-controllable four-terminal (4T) FinFETs with an aggressively thinned Si-fin thickness down to 8.5-nm have successfully been fabricated by using an orientation-dependent wet-etching technique, and the V/sub th/ controllability by gate biasing has systematically been confirmed. The V/sub th/ shift rate (/spl gamma/=-/spl delta/V/sub th///spl delta/V/sub g2/) dramatically increases with reducing Si-fin thickness (T/sub Si/), and the extremely high /spl gamma/=0.79 V/V is obtained at the static control gate bias mode for the 8.5-nm-thick Si-fin channel device with the 1.7-nm-thick gate oxide. By the synchronized control gate driving mode, /spl gamma/=0.46 V/V and almost ideal S-slope are achieved for the same device. These experimental results indicate that the optimum V/sub th/ tuning for the high performance and low-power consumption very large-scale integrations can be realized by a small gate bias voltage in the ultrathin Si-fin channel device and the orientation-dependent wet etching is the promising fabrication technique for the 4T FinFETs.

Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel

The FT-FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel have successfully been fabricated by using newly developed orientation-dependent wet etching. The flexible V/sub th/ controllability by using one of the double gates as a control gate and by the synchronized driving mode operation is experimentally confirmed. The developed processes are attractive for the fabrication of the advanced separate-gates FinFET for a flexible function VLSI circuit.

Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication

The titanium nitride (TiN) gate electrode with a tunable work function has successfully been deposited on the sidewalls of upstanding Si-fin channels of FinFETs by using a conventional reactive sputtering. It was found that the work function of the TiN (phi_TiN) slightly decreases with increasing nitrogen (N₂) gas flow ratio, R_N=N₂/(Ar+N₂) in the sputtering, from 17% to 100%. The experimental threshold voltage (V_th) dependence on the R_N shows that the more R_N offers the lower V_th for the TiN gate n-channel FinFETs. The composition analysis of the TiN films with different R_N showed that the more amount of nitrogen is introduced into the TiN films with increasing R_N, which suggests that the lowering of phi _TiN with increasing R_N should be related to the increase in nitrogen concentration in the TiN film. The desirable V_th shift from -0.22 to 0.22 V was experimentally confirmed by fabricating n⁺ poly-Si and TiN gate n-channel multi-FinFETs without a channel doping. The developed simple technique for the conformal TiN deposition on the sidewalls of Si-fin channels is very attractive to the TiN gate FinFET fabrication

Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching

A vertical ultrathin channel formation process for a vertical type double-gate (DG) MOSFET is proposed. Si wet etching using an alkaline solution has newly been found to be significantly retarded by introducing ion bombardment damage. We have also found that the ion-bombardment-retarded etching (IBRE) is independent of ion species and the implanted impurities can easily be transferred to be the dopants for source and drain regions of MOSFETs. By utilizing the IBRE, vertical type DG MOSFETs with a 12-nm-thick vertical channel were fabricated successfully. The fabricated vertical DG MOSFETs clearly exhibit the unique advantage of DG MOSFETs, i.e., high improvement of short-channel effect immunity by reducing the channel thickness. Thanks to the ultrathin channel, very low subthreshold slopes of 69.8 mV/dec. for a p-channel and 71.6 mV/dec for an n-channel vertical DG MOSFET are successfully achieved with the gate length of 100 nm.

Variability Analysis of TiN Metal-Gate FinFETs

Variability of TiN FinFET performance is comprehensively studied. It is found that the variation of the in the FinFET occurs and the standard deviations of the of nMOS and pMOS FinFETs are almost the same. From the analytical results, it is found that the variation of the TiN FinFET is due to the work function variation (WFV) of TiN metal gate. The WFV is also responsible for the on-current variation.

Cointegration of High-Performance Tied-Gate Three-Terminal FinFETs and Variable Threshold-Voltage Independent-Gate Four-Terminal FinFETs With Asymmetric Gate-Oxide Thicknesses

Cointegration of titanium nitride (TiN)-gate high-performance tied-gate three-terminal FinFETs with symmetric gate-oxide thicknesses (tox1=tox2=1.7 nm) and variable threshold-voltage Vth independent-gate four-terminal (4T) FinFETs with asymmetric gate-oxide thicknesses (tox1=1.7 nm for the driving-gate-oxide, and tox2=3.4 or 7.0 nm for the control-gate-oxide) has been successfully developed using conventional reactive sputtering, two-step Si-fin and gate-oxide formation, and resist etch-back processes. A significantly improved subthreshold slope and an extremely low OFF-state current Ioff are experimentally confirmed in the asymmetric gate-oxide thickness 4T FinFETs by increasing the control-gate-oxide thickness to twice or more the driving-gate-oxide thickness. The developed techniques are attractive for high-performance and low-power FinFET very large-scale integration circuits

Enhancing SRAM cell performance by using independent double-gate FinFET

SRAM cells with Vth-controllable independent double-gate (IDG) FinFETs have been successfully fabricated. The performance of the fabricated SRAM cell with various circuit topologies has been investigated comprehensively. Both a reduction of leakage current and an enhancement of read and write noise margins have been successfully demonstrated by introducing the IDG FinFETs into the SRAM cells.

On the gate-stack origin threshold voltage variability in scaled FinFETs and multi-FinFETs

The Vt variability in scaled FinFETs with gate length (Lg) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., work-function variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall channels fabricated by using the orientation dependent wet etching contribute to, not only the reduction of fin thickness (TSi) fluctuations, but also the reduction of gate-stack origin VTV. Moreover, it was experimentally found that the Vt of multi-FinFETs with the same gate area reduces with increasing the number of fins.

Experimental Evaluation of Effects of Channel Doping on Characteristics of FinFETs

We investigated channel doping in fin-type double-gate (DG) MOSFETs. We demonstrated through experiments that the threshold voltage was more sensitive to the dopants in the accumulation mode than in the inversion mode. We also found that significant deviation in the threshold voltage from the expected value arose in ultrathin fin-type DG MOSFETs. We attributed this phenomenon to the unexpected dopant loss from the ultrathin channels due to segregation. This finding means that careful doping adjustments must be made in ultrathin-channel devices.