Eiichi Suzuki

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10-12 or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.

A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS

For the people involved with multi-Gb/s chip-to-chip serial links, reducing power dissipation per Gb/s to less than 1mW/(Gb/s) (i.e., 1pJ/b) has been a long-held goal. Several years ago, the power dissipation of these links was in the range of about 10 to 20mW/(Gb/s). In 2007, Poulton et al. developed a 14mW 6.25Gb/s transceiver with power efficiency of 2.2mW/(Gb/s) [1]. Thereafter, there were some efforts aiming to reduce power of each building block in a transceiver [2, 3]. This paper presents a 12.3mW 12.5Gb/s complete transceiver (including CDR, MUX/DEMUX, and global clock distribution)in 65nm CMOS with power efficiency of 0.98mW/(Gb/s). To achieve low power, a resonant-clock distribution with distributed on-chip inductors and a low-swing voltage-mode driver with pulse-current boosting are used in the transmitter, while a symbol-rate comparator/phase detector using 4-stage sense amplifier and phase-rotating PLL with variable delay are used in the receiver.

A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order

A 10 Gb/s receiver with a digital CDR uses a track-and-hold-type linear phase detector (LPD) and charge-redistribution first-order ΔΣ modulator. It has low quantization error and high loop bandwidth due to the use of the LPD and maintains the advantages of a digital CDR such as low power consumption, small area, fast locking time, and low-jitter recovery clock because no internal VCO is needed. The CDR tracking bandwidth is 20 MHz and high-frequency jitter tolerance is 0.42 UIpp at 10-12 BER. Power consumption of LPD is 2.6 mW while the entire receiver consumes 65 mW.

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To evaluate an on-chip power supply noise waveforms for power integrity design, we have developed a technique for measuring on-chip voltage waveforms. To overcome trade-offs in voltage resolution and the measurable frequency band, we designed inverter chain circuits that change the lengths of series inverters: a short chain provides low frequency and high resolution, while a long chain provides high frequency and low resolution. We measured on-chip noise waveforms using a 90 nm CMOS test chip with a 50 -inverter chain circuit as small as 320 square micrometers, confirming that the circuit could achieve a voltage resolution of 1 mV and temporal resolution of 20 ps. The amplitude of the noise waveform generated by the noise source circuits is proportional to the activating ratio of the source, although resonance frequencies are virtually the same - 160 MHz - when the activating ratios change.

Modulator in 90-nm CMOS

A priority metric for IT equipment is proposed, and a method for extracting it from historical sensor data is devised. The proposed method consists of classification of cooling efficiency from sampled sensor data and calculation of the priority metric from statistics on these cooling-efficiency classes. A proof-of-concept experiment using the priority metric was conducted in a server room with a thermal environment including IT equipment units and cooling facilities. The results of the experiment indicate that IT-workload consolidation based on the proposed metric equalizes variation in server-room temperatures.

Measurement techniques for on-chip power supply noise waveforms based on fluctuated sampling delays in inverter chain circuits

This paper discusses new Vref designs for high-speed memory modules. Our designs include chip resistors in series with Vref traces that reduce the total noise. We confirmed reduced noise of half the original through experiments

Cooling efficiency aware workload placement using historical sensor data on IT-facility collaborative control

A CDR circuit and a phase detector are the key building blocks of high-speed interconnect systems. Today, most CDR circuits use bang-bang phase detectors. These phse detectors have several advantages, including low power consumption, a simple circuit structure, and compatibility with digital circuits [1,2]. However, bang-bang phase detectors have the intrinsic drawback of large quantization noise. Therefore, the CDR loop bandwidth must be relatively low to mitigate the effect of the quantization noise by time averaging. In particular, digital CDRs operated in a Δ-modulation loop are susceptible to quantization noise. On the other hand, linear phase detectors (LPDs) do not exhibit quantization noise and therefore by using them one can potentially increase the CDR bandwidth to achieve improved jitter tolerance. However, conventional LPDs, such as the Hogge phase detector, which detect the phase difference as a pulse width, cannot be easily incorporated in a digital CDR [3]. In this paper, a 10Gb/s receiver is described that is equipped with a track-and-hold-type LPD as well as a charge-redistribution ΔΣ modulator for incorporation in a digital CDR. The 10Gb/s receiver exhibited low quantization errors and high loop bandwidth that are due to the use of a linear phase detector while it maintains the advantages of a digital CDR circuit, such as low power consumption, small area occupation, fast locking time, and a low-jitter recovered clock because an internal VCO is not needed. The tracking bandwidth of the CDR circuit is about 20MHz, and the power consumption of the receiver is 65mW