Shinichi Ito

Optimization of optical properties for single-layer halftone masks

An algorithm necessary to decide the optimum optical properties of a single-layer halftone (HT) mask has been established. This paper reveals the relations between the refractive index n and the extinction coefficient k, and thickness d, and describes how to select optimum films among various materials. It has been found that SiNx is a good material for a single-layer HT mask for I-line (365 nm) and KrF (248 nm). The lithographic performance of an I-line SiNx HT mask for grouped line and space (L&S) patterns under annular illumination has also been demonstrated.

Sub-45nm resist process using stacked-mask process

The stacked-mask process (S-MAP) is a tri-level resist process by lithography and dry etching, which consists of thin resist, spin-on-glass (SOG), and spun-on carbon (SOC). However, as design rules progress below 60nm, two problems arise in the conventional S-MAP: 1) the deformation of SOC line pattern during SiO2 reactive ion etching (RIE), 2) the degradation of lithography performance due to high reflectivity at the interface between resist and SOG in high NA. In this study, we clarified the origin of the above problems and improved S-MAP materials and processes. Firstly, we found that the pattern deformation is induced by the inner stress due to volume expansion by fluorination during RIE, and that the deformation is suppressed by decreasing hydrogen content of SOC. Secondly, we developed new carbon-containing SOG that coexists with low reflectivity and acceptable etching performance. Using the above SOG and SOC, we developed a new S-MAP that shows an excellent lithography / etching performance in sub-45nm device fabrication.

Influence of the watermark in immersion lithography process

In the liquid immersion lithography, uses of the cover material (C/M) films were discussed to reduce elution of resist components to fluid. With fluctuation of exposure tool or resist process, it is possible to remain of waterdrop on the wafer and watermark (W/M) will be made. The investigation of influence of the W/M on resist patterns, formation process of W/M, and reduction of pattern defect due to W/M will be discussed. Resist patterns within and around the intentionally made W/M were observed in three cases, which were without C/M, TOK TSP-3A and alkali-soluble C/M. In all C/M cases, pattern defect were T-topped shapes. Reduction of pattern defects due to waterdrop was examined. It was found that remained waterdrop made defect. It should be required to remove waterdrop before drying, and/or to remove the defect due to waterdrop. But new dry technique and/or unit will be need for making no W/M. It was examined that the observation of waterdrop through the drying step and simulative reproduction of experiment in order to understand the formation mechanism of W/M. If maximum drying time of waterdrop using immersion exposure tool is estimated 90 seconds, the watermark of which volume and diameter are less than 0.02 uL and 350um will be dried and will make pattern defect. The threshold will be large with wafer speed become faster. From result and speculations in this work, it is considered that it will be difficult to development C/M as single film, which makes no pattern defects due to remained waterdrop.

LWR reduction in low-k1 ArF-immersion lithography

Line width roughness (LWR) reduction is a critical issue for low k1 ArF immersion lithography. Various approaches such as materials, exposure technology and the track process have been performed for LWR reduction during lithography process. It was reported that the post-development bake process had good performance for LWR reduction (1). However, the post-development bake process induced large CD change owing to the degradation of large isolated resist pattern. Therefore post-development process with small iso-dense bias is required in low k1 ArF immersion lithography. The resist smoothing process is one of the candidates for LWR reduction with small iso-dense bias. This method whereby the resist pattern surface is partially melted in organic-solvent atmosphere was shown to have a significant LWR reduction effect on resist patterns. This paper reports on the application of the resist smoothing process to the ArF immersion resist pattern after development. It was found that the resist smoothing process was effective to reduce LWR for ArF immersion resist. As a result of LWR trace from after development to after the hard mask etching process, the effect of LWR reduction with the resist smoothing process continued after the hard mask etching process. Furthermore CD change of large isolated patterns with the smoothing process was smaller than in the case of post-development bake process. We confirmed that the resist smoothing process is an effective method for decreasing LWR in ArF immersion lithography.

Immersion resist process for 32-nm node logic devices

Key issues of resist process design for 32nm node logic device were discussed in this paper. One of them is reflectivity control in higher 1.3NA regime. The spec for the reflectivity control is more and more severe as technology node advances. The target of reflectivity control over existent substrate thickness variation is 0.4%, which was estimated from our dose budget analysis. Then, single BARC process or stacked mask process (SMAP) was selected to each of the critical layers according to the substrate transparency. Another key issue in terms of material process was described in this paper, that is spin-on-carbon (SOC) pattern deformation during substrate etch process. New SOC material without any deformation during etch process was successfully developed for 32nm node stacked mask process (SMAP). 1.3NA immersion lithography and pattern transfer performance using single BARC

Pattern defect study using cover material film in immersion lithography

In immersion lithography, it is necessary that the surface of wafer has high hydrohybicity in order to prevent the residue of immersion fluid, i.e. pure water, that cause watermark defect. Usage of a cover material film over the resist film is effective to consistent with high hydrohybicity of the surface and high performance of resist film. But it was problem that much pattern deformation defects was observed with the use of an alkali-soluble type cover material film and an immersion exposure tool. As a result of the examination, it was identified that the fraction of film which caused the pattern deformation in the area of several micrometers were the fraction of the cover material. And the fractions of cover coat material were oriented in the coating defects of the cover material film and in the film peeling after scan of the immersion nozzle at the wafer bevel. The coating defects were improved with the chemical of the cover material. An adhesion process was effective to prevent the film peeling of cover material.

Effect of post development process for resist roughness

Recently, gate length variation such as Line Width Roughness (LWR) is severe problem in MPU. The LWR of resist pattern is mainly due to resist material and optical contrast. However it is hard to improve these factors. Many techniques have reported to decrease LWR, but there were no reports which process was more effective for improvement on LWR. Some methods were considered to improve resist roughness. This paper discusses about LWR of ArF resist in gate layer of 65 nm node device. We tied post bake process after development to smooth resist pattern surface by its surface tension. Recess process of resist roughness by using a pattern shrink film was also investigated. LWR’s were 36% and 26% decreased by post baking process and recess process, respectively. Post bake temperature was near resist melting point. From the consideration of thermal flow process, distance of smoothing force by surface tension is considered about several hundreds nm. Pattern shrink film is using acid catalysis reaction, so its distance of smoothing by acid diffusion is considered about one hundred nm. It is considered that effect of post development process is caused by distance of smoothing force. Moreover influence of those processes for lithographic performance will be evaluated.

Feasibility study of non-topcoat resist for 22nm node devices

Subsequent to 45 nm node, immersion lithography using topcoat process is approaching its next step for mass production. However, microfabrication using immersion topcoat leads to increase in cost due to increase in process steps. In order to deal with this problem, high throughput scanners equipped with a wafer stage which moves at higher speed are under development. Furthermore, as resist process compatible with such high speed scanners, non-topcoat resist is available and seems promising in reducing costs of the resist process. Non-topcoat resist contains hydrophobic additives which are eccentrically located near the film surface. Because non-topcoat resist enables the formation of a more hydrophobic surface, non-topcoat resist process is more suitable for high-speed scanning than topcoat resist process. In the topcoat process, the function of topcoat material and resist material is separated. That is, the resist material and the topcoat material are responsible for lithographic performance and immersion scanning performance, respectively. However, the non-topcoat resist is expected both performances. That is, the non-topcoat resist are required a fine resist profile, small LWR, and low development defects at high speed immersion scanning. In this paper, we report the application of non-topcoat resist in 22 nm node devices. We investigate the influence of hydrophobic additives on imaging performance in several base polymers. Additionally, the influence of chemical species, molecular weight and amount of hydrophobic additive are investigated. Scan performance is also estimated by dynamic receding contact angle using pin scan tool. 22nm node imaging performance is evaluated using Nikon NSRS610C. The surface characteristics and lithographic performance of non-topcoat resist for 22 nm node devices are discussed.

Defectivity reduction studies for ArF immersion lithography

Immersion lithography is widely expected to meet the manufacturing requirements of future device nodes. A critical development in immersion lithography has been the construction of a defect-free process. Two years ago, the authors evaluated the impact of water droplets made experimentally on exposed resist films and /or topcoat. (1) The results showed that the marks of drying water droplet called watermarks became pattern defects with T-top profile. In the case that water droplets were removed by drying them, formation of the defects was prevented. Post-exposure rinse process to remove water droplets also prevented formation of the defects. In the present work, the authors evaluated the effect of pre- and post-exposure rinse processes on hp 55nm line and space pattern with Spin Rinse Process Station (SRS) and Post Immersion Rinse Process Station (PIR) modules on an inline lithography cluster with the Tokyo Electron Ltd. CLEAN TRACKTM LITHIUS TM i+ and ASML TWINSCAN XT:1700Fi , 193nm immersion scanner. It was found that total defectivity is decreased by pre- and post-exposure rinse. In particular, bridge defects and large bridge defects were decreased by pre- and post-exposure rinse. Pre- and post-exposure rinse processes are very effective to reduce the bridge and large bridge defects of immersion lithography.

Dissolution performance of device pattern with low-impact development

For low-k1 lithography, high accurate control of the development process is required. For that purpose, low- impact dispensing is one of the most effective approaches. In that process, development time differs between start and end position of nozzle-scan. To reduce the time lag, the nozzle-scan-speed of 140mm/s was selected. But critical dimensions (CD) offset that depends on scan-direction was detected. From the results of the CD and dissolution performances for three resists, we found that the pull-back flow of the developer was the main cause of the CD offset. Thus, it is important that the developer does not flow by its pull-back-force. By observing and analyzing the flow of the dissolution product with a video camera, the best condition of the scan-speed (=60 mm/s) was selected. Under this nozzle-scan condition, the dissolution rates did not depend on the scan-direction of the dispenser-nozzle. As a result, the small CD offset could be observed for 200nm L&S patterns.