Shinji Mikami

A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC Under DVS Environment

This paper proposes a voltage-control scheme for an SRAM that makes a minimum operation voltage down to 0.3 V even on a future memory-rich SoC. A self-aligned timing control guarantees stable operation in a wide range of Vdd under DVS environment. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that 30% power reduction is achieved at 100 MHz. The area overhead is only 5.6%

A Wireless-Interface SoC Powered by Energy Harvesting for Short-range Data Communication

This paper describes the design and estimation of a wireless-interface SoC for wireless battery-less mouse with short-range data communication capability. It comprises an RF transmitter and microcontroller. An SoC, which is powered by an electric generator that exploits gyration energy by dragging the mouse, was fabricated using the TSMC 0.18-mum CMOS process. Features of the SoC are the adoption of a simple FSK modulation scheme, a single-end configuration on the RF transmitter, and the specific microcontroller design for mouse operation. We verified that the RF transmitter can perform data communication with a 1-m range at 2.17 mW, and the microcontroller consumes 0.03 mW at 1 MHz, which shows that the total power consumption in the SoC is 2.2 mW. This is sufficiently low for the SoC to operate with energy harvesting

Isochronous MAC using Long-Wave Standard Time Code for Wireless Sensor Networks

This paper proposes isochronous-MAC (I-MAC), which utilizes low-frequency radio waves time synchronization for sensor networks. Using IMAC, based on the low power listening (LPL), all sensor nodes wake and listen channel periodically and synchronously. Since a sender can easily predict wakeup time of an intended receiver, it can shorten the length of preamble to make the receiver prepare for reception of the following data packet. This saves power consumption for the sender to rendezvous with the receiver. In the paper, we use an analytical model to investigate the impact of the data transmission frequency, the number of neighboring nodes, the wakeup period, the clock drift, and the time-synchronization frequency on the power consumption for consideration of the power overhead to perform the time synchronization. Those results demonstrate that I-MAC allows determination of any arbitrary wakeup period without much difficulty, whereas LPL requires a much more careful setting of the wakeup period because its optimum wakeup period is sensitive to the frequency of data transmission as well as to the number of neighboring nodes. Therefore, IMAC has a great potential to reduce the power consumption in most situations compared with LPL, in spite of the overhead to perform time synchronization.

Aggregation efficiency-aware greedy incremental tree routing for wireless sensor networks

SUMMARY In most research work for sensor network routings, perfect aggregation has been assumed. Such an assumption might limit the application of the wireless sensor networks. We address the impact of aggregation efficiency on energy consumption in the context of GIT routing. Our questions are how the most efficient aggregation point changes according to aggregation efficiency and the extent to which energy consumption can decrease compared to the original GIT routing and opportunistic routing. To answer these questions, we analyze a two-source model, which yields results that lend insight into the impact of aggregation efficiency. Based on analytical results, we propose an improved GIT: “aggregation efficiency-aware GIT,” or AGIT. We also consider a suppression scheme for exploratory messages: “hop exploratory.” Our simulation results show that the AGIT routing saves the energy consumption of the data transmission compared to the original GIT routing and opportunistic routing.

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30% can be achieved at 100 MHz. In a 65-nm 64-Mb SRAM, a 74% power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1%, and area overhead is 5.6%.

Cross-Layer Design for Low-Power Wireless Sensor Node Using Long-Wave Standard Time Code

We propose isochronous-MAC (I-MAC) using the long-wave standard time code, and introduce cross-layer design for a low-power wireless sensor node with I-MAC. I-MAC has a periodic wakeup time synchronized with the actual time, and thus requires a precise timer. However, a frequency of a crystal oscillator varies along with temperature, from node to node. We utilize a time correction algorithm to shorten the time difference among nodes. Thereby, the preamble length in I-MAC can be minimized, which saves a communication power. For further power reduction, a low-power crystal oscillator is also proposed, as a physical-layer design. We implemented I-MAC on an off-the-shelf sensor node to estimate the power saving, and verified that I-MAC reduces 81% of the total power, compared to low power listening.