Hidehiro Fujiwara

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies

FinFET technology has been adopted in the 16nm node because it provides superior lon/loff ratio, short-channel effect and local variation [1,2]. 2P-SRAM, which offers simultaneous read and write operations, is widely used for media processing because of its high operating efficiency. However, 2P-SRAM using the conventional 2P8T cell has a read-disturb issue, when both read wordline (RWL) and write word-line (WWL) are asserted simultaneously in the same row [3]. Furthermore, read-disturb becomes worse in FinFET technology compared with classical planar technology. In order to overcome these problems, we develop a disturb-current-free (DCF) 2P8T cell with PMOS write pass-gates and peripheral assist circuits to further improve its performance.

A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications

In low voltage SRAM for IoT application, although static noise margin (SNM) and write margin (WM) decide VMIN, Icell / Ioff ratio and Icell are also important in order to keep performance and achieve better operating efficiency. We propose a new mixed Vth RP design which can achieve better Icell and Icell / Ioff ratio. Furthermore, combination of the proposed mixed Vth and boosted read wordline (RWL) scheme improves the worst case bitline delay time by 72.3% at 0.45V. In the measurement results, we confirmed a minimum operating voltage (VMIN) for the 64 Kb SRAM of 0.370 V with 99% yield at room temperature.