Shinji Miyano

A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator

This DRAM macro is suitable for a memory generator implementation. The article shows the expandable floor layout scheme (EFLS) of the DRAM macros. A macro architecture that consists of several banks has a disadvantage that the macro size becomes large, because each bank has peripheral circuits for independent operation. The EFLS eliminates this redundancy by sharing the peripheral circuits among the expansion units of the memory array. Two types of floor layouts are supported by EFLS. One is simple I/O type. The other is doubled I/O type. In both of the arrangements, a DRAM macro is formed by combination of 1 Mb memory array segments and peripheral blocks. Each block is manually designed so the macro size is minimized when all the blocks are combined together. Peripheral circuits that can be shared among 1 Mb segments are placed in the peripheral blocks to save the area.

A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM

To realize high data-transfer rate in random access, several kinds of DRAMs with on-chip cache memory have been proposed. These DRAMs rely on locality of access to achieve the highest speed. However, in some graphic applications where sufficient locality of access is not expected, such DRAMs will not greatly accelerate system performance. Embedded memories have benefits for such applications due to their wide data bus and band width. The 8 Mb embedded DRAM presented in this paper provides 1.6 GB/s data transfer rate and realizes 10 ns cycle random access without page fault delay.

An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation

We propose an IBA scheme based on a pull-out detection, which is suitable for implementing in a circuit. The scheme is implemented in a driver IC that is part of a module with an RF MEMS variable capacitor. No failures are observed over 108 cycles at 85degC, which is an accelerated charging condition.

Misleading energy and performance claims in sub/near threshold digital systems

Many of us in the field of ultra-low-Vdd processors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates five major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower Vdd with a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different Vth definitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memorys Vdd and energy could scale as well as standard cells, iv) use the highest temperature as the worst timing corner as in the super-threshold, but in fact negative temperature becomes much more detrimental in the sub/near threshold regime, v) pursue just-in-need Vdd to compensate effects of PVT, but without considering the high energy loss on DC-DC converters. Therefore, the actual energy benefit from using a sub/near threshold Vdd can be greatly overestimated. This work provides some design guidelines and silicon evidence to ultra-low-Vdd systems. The outlined pitfalls also shed light on future directions in this field.

Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor

8T-SRAM cell with asymmetric pass gate transistor by local electron injection is proposed to solve half select disturb. Two types of electron injection scheme: both side injection scheme and self-repair one side injection scheme are analyzed comprehensively for 65nm technology node 8T-SRAM cell and also for 6T-SRAM cell. This paper shows that in the 6T-SRAM with the local injected electrons [4] the read speed degrades by as much as 6.3 times. In contrast, the proposed 8T-SRAM cell with the self-repair one side injection scheme is most suitable to solve the conflict of the half select disturb, write disturb and read speed. In the proposed 8T-SRAM, the disturb margin increases by 141% without write margin or read speed degradation. The proposed scheme has no process or area penalty compared with the standard CMOS-process 8T-SRAM.

Direct measurements, analysis, and post-fabrication improvement of noise margins in SRAM cells utilizing DMA SRAM TEG

A special device-matrix-array (DMA) TEG of 16k bit SRAM cells has been designed. Static noise margins (SNM) and 6 transistors in cells are directly measured and their fluctuations are examined. It is found for the first time that one-side SNM follows the normal distribution up to ±4σ. It is also found that the cell stability is worse than circuit simulation using Vth of measured 6 transistors. Furthermore, the post-fabrication self-convergence scheme by NBTI stress is applied to DMA SRAM TEG and the cell stability improvement is demonstrated experimentally for the first time.

A 65nm low-power embedded DRAM with extended data-retention sleep mode

An extended data retention (EDR) sleep mode with ECC and MT-CMOS is proposed for embedded DRAM power reduction. In sleep mode, the retention time improves by 8 times and the leakage current is reduced to 13% of the normal operation mode. Since ECC scrubbing operates only in the EDR sleep mode, read/write performance is not degraded. A 65nm low-power embedded DRAM macro featuring 400MHz operation and 0.39mW of data-retention power is realized

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus

A novel dataline redundancy suitable for an embedded DRAM macro with wide data bus is presented. This redundancy reduces the area required for spare cells from 6 to 1.6% of the area required for normal cells and improves chip yield from 50 to 80%. In addition, it provides a high-speed data path. An embedded DRAM macro adopting the redundancy achieves 200-MHz operation and provides 51.2-Gbit/s bandwidth. It has been fabricated with 0.25-/spl mu/m technology.

Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme

We found the dynamic-energy increase in SRAM caused by VDD reduction under 0.7V. This is caused by the random variability and the total (dynamic + leakage) energy increase is estimated to be 95% at 0.5V. A Bitline Amplitude Limiter capable of compensating this energy degradation is proposed. This limiter reduces dynamic energy by suppressing excess bitline amplitude. And it reduces leakage automatically even during the operation. The speed penalty for introducing this circuit is estimated to be 7%. And the area penalty is less than 2%. The total energy reduction of 26% has been confirmed with simulations at 0.5V. The circuit has been implemented with 40nm CMOS technology and the energy reduction of 19% is confirmed by measurements.

Universal Test Interface for embedded-DRAM testing

Because the configurations of embedded DRAM macros vary for each product, designers normally must customize the test circuitry for each product. The authors have developed circuitry (Universal Test Interface) that unifies testing regardless of the DRAM configuration and the number of macros on a chip. The Universal Test Interface alleviates the contradiction inherent in embedded DRAM testing.