Kousuke Miyaji

Voltage gain dependence of the negative differential conductance width in silicon single-hole transistors

The full width at half maximum (FWHM) of the negative differential conductance (NDC) characteristics in room temperature (RT)-operating silicon single-hole transistors (SHTs) has been studied by experiments and calculations. It is found that when the voltage gain of the SHT is higher, sharper NDC and smaller FWHM are achieved. Lower drain coupling is considered to be the main reason for the small FWHM in a resonant tunneling system of RT-operating SHTs. FWHM of NDC of as small as 95mV has been obtained in a SHT with the gain of as high as 5.2 at RT, which is the highest value of the gain ever reported. The device is in the form of an ultranarrow wire channel metal oxide semiconductor field-effect transistor, which shows large Coulomb blockade oscillations at RT and has extremely small drain capacitance due to its ultranarrow channel structure. NDC can now be designed by device parameters, showing further potential for application to low-voltage, low-power NDC circuits.

Experimental study of mobility in [110]- and [100]-directed multiple silicon nanowire GAA MOSFETs on (100) SOI

Experimental investigations of silicon nanowire mobility characteristics on (100) SOI as shrinking nanowire width to sub-10 nm are reported. Accurate mobility estimations by advanced split CV method for 50~1000 nanowires are performed. For the first time, electron and hole mobility in [100]-directed nanowires are studied and compared with [110] nanowires. It is shown that both electron and hole mobility decreases monotonically and electron mobility of [100]-directed nanowire tends to be comparable to that of [110]-directed nanowire as decreasing nanowire width.

Compact analytical model for room-temperature-operating silicon single-electron transistors with discrete quantum energy levels

A compact and analytical model for silicon single-electron transistors (SETs) considering the discrete quantum energy levels and the parabolic tunneling barriers is proposed. The model is based on a steady-state master equation that considers only the three most probable states derived from ground level and the first excited level for each number of electrons in the dot to reduce the complexity while accounting for the quantum-level spacing and multiple peaks in Coulomb oscillation. Negative differential conductance (NDC) characteristics and aperiodic Coulomb oscillations due to nonuniform quantum-level spacings can be reproduced in this model. The model was compared with measurements, and good agreement was obtained. Simulations of some basic circuits that utilize NDC are successfully carried out by applying our model to the HSPICE circuit simulation. Our model can provide suitable environments for designing CMOS-combined room-temperature-operating highly functional SET circuits.

Extremely high flexibilities of Coulomb blockade and negative differential conductance oscillations in room-temperature-operating silicon single hole transistor

A unique feature of the extremely long-range-extended blockade regime with its shape of a long stick, where the Coulomb blockade oscillation and negative differential conductance peak-positions can be systematically and precisely modulated for both extremely-wide VG and VD ranges, was clearly observed in a room-temperature-operating silicon single hole transistor. These results originate from the large quantum level spacing, large tunnel-barrier height, small tunnel-barrier curvature, small bias-induced barrier modulation, and large voltage gain, attributing to the formation of an ultrasmall dot in the gently sloped tunnel barriers along the [100] Si nanowire channel having the large subband modulation.

A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD

A hybrid 3D-TSV ReRAM/MLC NAND SSD with cold data eviction (CDE) algorithm is proposed. In the proposed hybrid SSD, the lifetime and energy consumption are dominated by MLC NAND flash memory due to ReRAMs high endurance and low power consumption. In addition, partial page overwrites are possible in ReRAM. Thus, the write accesses to MLC NAND flash memory are largely reduced by storing hot data in ReRAM. As a result, the SSD energy consumption decreases and the lifetime is prolonged. With the CDE algorithm, a page-level adaptive data migration is achieved, which is transparent to the file system. Compared to the previous work, 8-times write throughput increase, 83% energy reduction and 6.5-times longer longevity are achieved with 3D-TSV technology. Moreover, from the experimental results, the data eviction should be triggered when ReRAM free space ratio decreases to a range of 8%-20%. Hence, the eviction frequency is adaptive to the data pattern in the hybrid SSD. The experimental results also suggest the requirements for ReRAM. To obtain the best effect, both the read and write latency of ReRAM should be below 3 μs for 512 Bytes.

Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor

8T-SRAM cell with asymmetric pass gate transistor by local electron injection is proposed to solve half select disturb. Two types of electron injection scheme: both side injection scheme and self-repair one side injection scheme are analyzed comprehensively for 65nm technology node 8T-SRAM cell and also for 6T-SRAM cell. This paper shows that in the 6T-SRAM with the local injected electrons [4] the read speed degrades by as much as 6.3 times. In contrast, the proposed 8T-SRAM cell with the self-repair one side injection scheme is most suitable to solve the conflict of the half select disturb, write disturb and read speed. In the proposed 8T-SRAM, the disturb margin increases by 141% without write margin or read speed degradation. The proposed scheme has no process or area penalty compared with the standard CMOS-process 8T-SRAM.

Electron Mobility in Silicon Gate-All-Around [100]- and [110]-Directed Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor on (100)-Oriented Silicon-on-Insulator Substrate Extracted by Improved Split Capacitance–Voltage Method

In this paper, we report our experimental study on electron mobility in silicon gate-all-around (GAA) nanowire metal–oxide–semiconductor field-effect transistors (MOSFETs) on (100)-oriented silicon-on-insulator (SOI) substrates. With the aim of accurate mobility measurement, the improved split capacitance–voltage (C–V) method is utilized to remove parasitic resistance and capacitance. Accurate electron mobility in [100]-directed nanowires is achieved for the first time and shows high electron mobility that approaches the (100) bulk universal curve, while electron mobility in [110]-directed nanowires shows large degradation from the universal curve. The underlying physical mechanisms of mobility behaviors in nanowires on (100)-oriented SOI substrates are also investigated.

Control of full width at half maximum of Coulomb oscillation in silicon single-hole transistors at room temperature

The full width at half maximum (FWHM), the sharpness of the Coulomb blockade oscillation in a single-hole transistor (SHT), has been controlled at room temperature by means of substrate capacitance control using substrate depletion and accumulation/inversion. When the substrate is depleted, the substrate capacitance is lower than when it is accumulated or inverted, resulting in a smaller FWHM. The SHT was fabricated on a thin buried oxide silicon-on-insulator substrate whose initial thickness was 10nm. Low temperature measurements have been performed on another SHT to support the results. The control of the sharpness in a single-charge transistor (SCT) may add further functionality to the SCT.

SCM capacity and NAND over-provisioning requirements for SCM/NAND flash hybrid enterprise SSD

The required storage class memory (SCM) capacity and NAND over-provisioning (OP) for SCM/NAND hybrid enterprise solid state drive (SSD) are evaluated for various storage workloads. From the worst case simulations (hot and random data intensive workloads), it is found that less than 8% SCM/NAND capacity ratio with below 25% NAND OP is sufficient assuming SCM bit cost is 10-times as high as that of NAND. Other workloads with the exception of all-cold-data case can use less than 4% SCM/NAND capacity ratio with 100% NAND OP. According to the analyses, SCM tends to be cost-effective for the hot workload rather than the random one. Furthermore, the effect of NAND organization on the hybrid SSD write performance is considered. NAND organization with an 8-128KB page size and 1-8MB block size provides the best performance for the hot and random data intensive workloads. From the energy point of view, SCM/NAND hybrid SSD allows larger NAND page sizes compared with NAND-only SSD.

Control Gate Length, Spacing and Stacked Layer Number Design for 3D-Stackable NAND Flash Memory

Scaling and device design for 3D-stackable NAND (3D NAND) flash memory are investigated. Control gate length (Lg) and spacing (Lspace) are paid attention since they can be separately varied in 3D NAND and significantly affect the cell area of the 3D NAND as well as the electrical characteristics. The requirements for the Lg and Lspace are derived from the 3D device simulation and the cell size to compete with the planar NAND. The simulations reveal that Lg=Lspace=20nm (40nm layer pitch) is achievable for BiCS type 3D NAND with the 90nm diameter hole. Programming voltage can be also reduced from 20V to 17V. Lg and Lspace should be the same to cope with the tradeoff between memory window and disturbance. If the number of stacked layers is 18 with the layer pitch of 40nm, the effective cell size of the 3D NAND corresponds to that of 15nm planar NAND technology.