Shinji Tadaki

Photostimulated luminescence of BaBr2 : Eu

Abstract BaFBr : Eu is a well-known photostimulated luminescence (PSL) phosphor used as an X-ray image receptor for digital radiography systems. We fabricated BaBr 2 : Eu and confirmed that it is also a PSL phosphor. An image stored using BaBr 2 : Eu can be read using several different wavelengths; a 780 nm semiconductor laser is particularly attractive because it is very small and high powered.

51.2: Improvement of Reflectance and Contrast Ratio of Low-Power-Driving, Bendable, Color Electronic Paper Using Ch-LCs

We have newly developed flexible electronic paper using an easily-controlled adhesive column spacer that forms cell gaps and improves the aperture ratio without using bead spacers. The reflectance of this new, flexible, full-color prototype with low- power driving is 33%, its contrast is over 6, and it can display 262,144 colors.

25.2: Analysis of Deterioration of BaMgAl10O17:Eu2+ Phosphor for Plasma Display Panels

Using TEM, we studied the amorphous phase on a BaMgAl10O17:Eu2+ phosphor surface deteriorated by VUV irradiation. This paper describes growth of the amorphous phase and shows that irradiation from the a-axis of the phosphor crystal intensively increased the growth of the amorphous phase, compared with the results of irradiation from the c-axis.

Study of Chip Stacking Process and Electrical Characteristic Evaluation of Cu Pillar Joint Between Chips Including TSV

Three-dimensional chip stacking is a useful integration technology for improving electrical performance. In this study, we manufactured two different-sized stacked chips and examined the stacking process and electrical properties of a Cu pillar joint with a through-silicon via (TSV). To achieve alignment accuracy, a stacking process using reflow with reduction atmosphere was evaluated. As a result, the reflow process ensured bonding accuracy and the successful joining of a CuSn intermetallic compound. To determine electrical characteristics, we evaluated the electro-migration of the Cu pillar intermetallic compound (IMC) joint, which resulted in problems with small inter-chip connection. It was clarified that there was no damage to the TSV or TSV joint from the current flow, and the lifetime of the Cu pillar joint constructed with a CuSn IMC was determined to have improved by several times compared with a conventional Cu pillar and a solder joint.

Reliability studies on micro-joints for 3D-stacked chip

Three-dimensional chip stacking technology is expected to be a powerful method for achieving a short wiring distance between chips, and high-density integration of the functions in the chip, and to achieve the next generations high-performance large-scale integration (LSI). Each vertically stacked chip is connected by a metal line that penetrates in Si that is called a TSV (Through Silicon Via). In the present study, the test element group (TEG) in the double-layered structure where a TSV was formed was made for trial purposes to develop elemental technology related to the correlation, design conditions, characteristics, and reliability that connected it to the stacking process conditions, and the thermal cycle test was executed. The junction disconnected by the thermal cycle test was observed, and the cause of the disconnection was presumed.

Thermal stress reliability of copper through silicon via interconnects for 3D logic devices

For 3D-LSI devices using the through silicon via (TSV) process, there are many reliability issues regarding the large thermal-mechanical stress and deformation volume changes caused by mismatch of the thermal expansion coefficients (CTEs) between the Cu and Si substrate in the device active area. In this paper, we investigated the TSV leakage current in metal-insulator-semiconductors and studies MOSFET device characteristics to manage manufacturing quality based on stress propagation of Cu-TSVs by thermal loading in the operating temperature range (−50 to 80 °C) and relatively high process temperature range (250 to 400 °C). The stress induced leakage current and MOSFET mobility change showed a relationship between expansion and contraction deformation of Cu under the thermal loading conditions. These results show that Cu/Si interface formation quality is high although there is major TSV metallization. Furthermore, it was found that precise estimation is important to designing the keep out zone (KOZ) in consideration of the real operating temperature.

44.2: Super‐High‐Resolution FLC Display Based on Field Sequential Color Method with Low Driving Voltage

We investigated the effect of a storage capacitor (Cs) on the driving voltage in ferroelectric liquid crystal (FLC) displays by which a TFT array drives the FLCs. The addition of Cs enabled a decrease in the driving voltage. When spontaneous polarization (Ps) was large, the decrease in the driving voltage was larger than when Ps was small. We were able to use 5V as the driving voltage of an FLC display. According to the prototype we built based on the field sequential color (FSC) method, we were able to achieve the characteristics of super-high-resolution (318 ppi), high-speed response (300 μs), and high color purity (greater than the NTSC standard).

Study of MOSFET thermal stability with TSV in operation temperature using novel 3D-LSI stress analysis

A large thermal-mechanical stress caused by the mismatch of thermal expansion coefficients (CTEs) between the copper and silicon substrate occurs in the active area of the stacked 3D device using the through-silicon via (TSV). Therefore, the study of TSV-induced stress is of fundamental importance in our understanding of the keep-out zone (KOZ). We investigated the metal-oxide-semiconductor field-effect transistor (MOSFET) thermal stability of a device operated by combining Technology Computer-Aided Design — Simulation Program with Integrated Circuit Emphasis (TCAD-SPICE) stress analysis and an actual ring oscillator circuit (ROSC) nearby TSVs. The MOSFET drain current (Id) fluctuates in response to the behavior of the Si stress caused by the TSVs. However, it was found that the simulation and test measurement results showed that the KOZ becomes smaller because the electric charge/discharge is canceled in the case of a p/n MOS inverter circuit. This study showed the importance of the design of the KOZ, which includes the temperature fluctuation phenomenon in a real integrated circuit device operation.