Seiki Sakuyama

Reflow soldering using selective infrared radiation

We developed a new reflow soldering technique, which uses selective infrared radiation. We use an aluminum-oxide heater and a halogen-heater for the IR sources. The aluminum-oxide heater radiates intensive infrared rays between about 5 to 8 /spl mu/m. This wavelength is readily absorbed by a glass-epoxy substrate. The halogen-heater radiates intensive infrared rays between about 1 to 2 /spl mu/m. This wavelength is readily absorbed by the resin used in quad flat packages (QFPs). By using these heaters, we can selectively heat the devices on a printed circuit board (PCB). The temperature difference between the PCB substrate and the large QFPs was reduced to about half that for conventional heating. This reduced temperature difference allows us to reflow solder the PCB at about 215/spl deg/C. This temperature is the same temperature as vapor phase soldering and is about 20/spl deg/C to 30/spl deg/C lower than conventional infrared reflow soldering.

A low temperature Cu-Cu direct bonding method with VUV and HCOOH treatment for 3D integration

In this paper, a low temperature Cu-Cu direct bonding method is demonstrated even at 175 degree C, which is less than solder melting point, by using fine crystalized bump surface and dedicated surface treatments. Our technique includes introducing fine crystal structure on Cu bump surface by ultra-precision cutting for bump planarization, not using conventional CMP method. This fine crystal structure can easily recrystallize at 150 degree C condition, which can provide a metallurgical interdiffusion between Cu-Cu interfaces. In addition, surface treatment is also crucial for direct Cu-Cu bonding. In this study, we investigated formic acid (HCOOH) and vacuum ultraviolet (VUV) irradiation effects on die shear strength. Cut Cu bump with VUV and HCOOH condition at 175 degree C not only showed high bonding strength, but also exhibited solid diffusion at interface while Cut Cu with HCOOH condition showed clear interface.

Study of Chip Stacking Process and Electrical Characteristic Evaluation of Cu Pillar Joint Between Chips Including TSV

Three-dimensional chip stacking is a useful integration technology for improving electrical performance. In this study, we manufactured two different-sized stacked chips and examined the stacking process and electrical properties of a Cu pillar joint with a through-silicon via (TSV). To achieve alignment accuracy, a stacking process using reflow with reduction atmosphere was evaluated. As a result, the reflow process ensured bonding accuracy and the successful joining of a CuSn intermetallic compound. To determine electrical characteristics, we evaluated the electro-migration of the Cu pillar intermetallic compound (IMC) joint, which resulted in problems with small inter-chip connection. It was clarified that there was no damage to the TSV or TSV joint from the current flow, and the lifetime of the Cu pillar joint constructed with a CuSn IMC was determined to have improved by several times compared with a conventional Cu pillar and a solder joint.

Reliability studies on micro-joints for 3D-stacked chip

Three-dimensional chip stacking technology is expected to be a powerful method for achieving a short wiring distance between chips, and high-density integration of the functions in the chip, and to achieve the next generations high-performance large-scale integration (LSI). Each vertically stacked chip is connected by a metal line that penetrates in Si that is called a TSV (Through Silicon Via). In the present study, the test element group (TEG) in the double-layered structure where a TSV was formed was made for trial purposes to develop elemental technology related to the correlation, design conditions, characteristics, and reliability that connected it to the stacking process conditions, and the thermal cycle test was executed. The junction disconnected by the thermal cycle test was observed, and the cause of the disconnection was presumed.

Thermal stress destruction analysis in low-k layer by via-last TSV structure

Investigation of the thermo-mechanical stress by using finite element analysis (FEA) and the destruction verification with thermal cycle (TC) test were carried out. It was found that the back end of line (BEOL) dielectric layer near the through silicon via (TSV) was cracked in case of a RT-400 °C heat cycle. Thermo-mechanical stress concentration at the TSV landing area has been confirmed by the results of FEA simulation. Dielectric layer cracking was caused at interface between the dielectric layer and edge corner of the land metal (M1) contact pad connected with the TSV. And the slit voids at the TSV sidewall were observed on the area of insufficient of side coverage of the titanium (Ti) metal barrier liner at the TSV bottom. The BEOL deformation of the metal contact area was also clear that the low-k cracks tend to occur at non constraint condition of the TSV sidewall as the slit void. In this paper shows that the interface becomes free surface as non-constrained condition caused by poor liner coverage, and it was insufficient interface adhesion to suppress the thermal expansion deformation of copper. This study provides that low-k layer cracking can be avoided by adopting optimized stress dispersion design to the BEOL low-k/copper with TSV landing pad structure.

Cu/Adhesive Hybrid Bonding at 180 °C in H-Containing HCOOH Vapor Ambient for 2.5D/3D Integration

Bump-less Cu/adhesive hybrid bonding is a promising technology for 2.5D/3D integration. The remaining issues of this technology include high Cu–Cu bonding temperature, long thermal-compression time (low throughput), and large thermal stress. In this paper, we investigate a Cu-first hybrid bonding process in hydrogen(H)-containing formic acid (HCOOH) vapor ambient, lowering the bonding temperature to 180 °C and shortening the thermal-compression time to 600 s. We find that the H-containing HCOOH vapor pre-bonding treatment is effective for Cu surface activation and friendly to adhesives at treatment temperature of 160–200 °C. The effects of surface activation (temperature and time) on Cu–Cu bonding and cyclo-olefin polymer (COP) adhesive bonding are studied by shear tests, fracture surface observations, and interfacial observations. Cu/adhesive hybrid bonding was successfully demonstrated at a bonding temperature of 180 °C with post-bonding adhesive curing at 200 °C.

Thermal stress reliability of copper through silicon via interconnects for 3D logic devices

For 3D-LSI devices using the through silicon via (TSV) process, there are many reliability issues regarding the large thermal-mechanical stress and deformation volume changes caused by mismatch of the thermal expansion coefficients (CTEs) between the Cu and Si substrate in the device active area. In this paper, we investigated the TSV leakage current in metal-insulator-semiconductors and studies MOSFET device characteristics to manage manufacturing quality based on stress propagation of Cu-TSVs by thermal loading in the operating temperature range (−50 to 80 °C) and relatively high process temperature range (250 to 400 °C). The stress induced leakage current and MOSFET mobility change showed a relationship between expansion and contraction deformation of Cu under the thermal loading conditions. These results show that Cu/Si interface formation quality is high although there is major TSV metallization. Furthermore, it was found that precise estimation is important to designing the keep out zone (KOZ) in consideration of the real operating temperature.

Analyzing and modeling methods for warpages of thin and large dies with redistribution layer

Analyzing and modeling methods for warpages including cylindrical deformations are discussed in large-area dies with redistribution layers (RDLs) and thin 50-µm-thick Si substrates. The buckling behavior of warpage, a deformation transition from spherical to cylindrical, strongly depends on the lateral sizes of the dies and the RDL structures, and can be calculated using the analytical model of the nonlinear plate theory. The equivalent stress values are introduced to simplify RDL structures by applying the model to measured curvatures of homogeneous patterned samples. Area densities of Cu are a good index for evaluating die warpage even for inhomogeneous patterned RDLs.

Development of second-level connection method for large-size CPU package

This paper reports on second-level interconnection development for a large-scale Ball Grid Array (BGA) package. Generally, control of warpage becomes a problem as BGA packages become larger. To solve this problem, the following two measures were executed. The first was adoption of a low-temperature solder, and the second was warpage control using a heat spreader as a fixture. We were able to decrease the reflow temperature to 200°C by applying the low-temperature solder, and the effect was a warp reduction of 200 μm. Moreover, the shape of the heat spreader was optimized through a thermal-stress simulation, obtaining a warp reduction of 100 μm. Verification with a test vehicle was executed, no short/opening was observed, and the results of a thermal cycle test and simulation confirmed there was no problem in reliability.

Cu/adhesive hybrid bonding through a Cu-first bonding approach by using H-containing HCOOH vapor surface treatment

Cu/adhesive hybrid bonding is a promising technology to fabricate 3D integrated microsystems with ultra-fine pitch and short vertical interconnects, low electrical resistance, and high reliability. The main remaining issues of this technology include bonding temperature mismatch between Cu-Cu (350–400 °C) and adhesive (typically ≤250 °C), long thermal-compression time (low throughput), and high thermal stress. In this paper, we present a sub-200 °C Cu/adhesive hybrid bonding method. By using H-containing HCOOH vapor pre-bonding treatment, the bonding temperature is lowered to 180–200 °C and the thermal-compression time is shortened to 600 s, enabling a Cu-first hybrid bonding approach. Cu/adhesive hybrid bonding was successfully demonstrated at bonding temperature of 180 °C. The effects of prebonding treatment temperature and time on Cu-Cu bonding and cyclo-olefin polymer (COP) adhesive bonding are investigated in detail.