Shinpei Yamaguchi

Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process

Novel channel-stress enhancement technology on damascene gate process with eSiGe S/D for pFET is demonstrated. It is found for the first time that the damascene gate process featured by the dummy gate removal is more effective in increasing channel strain than the gate-1st process as an embedded SiGe stressor technique is used. Furthermore, an additional channel recess related to the damascene process is shown to enhance channel strain, resulting in a 14% Ion improvement at Ioff = 100 nA/um. We propose combining these strain techniques with high-k/metal gate stacks for low-power and high-performance pFETs.

High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates

CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6 nm were obtained for the nFETs and pFETs. The further integration of pFETs on (110) substrates contributed to a higher drive current of 830 muA/mum. These performances were realized under low gate leakage currents of 0.03 A/cm2 and below

High-Performance Metal/High-

Newly proposed mobility-booster technologies are demonstrated for metal/high-k gate-stack n- and pMOSFETs. The process combination of top-cut SiN dual stress liners and damascene gates remarkably enhances local channel stress particularly for shorter gate lengths in comparison with a conventional gate-first process. Dummy gate removal in the damascene gate process induces high channel stress, because of the elimination of reaction force from the dummy gate. PFETs with top-cut compressive stress liners and embedded SiGe source/drains are performed by using atomic layer deposition TiN/HfO2 gate stacks with Tinv=1.4 nm on (100) substrates. On the other hand, nFETs with top-cut tensile stress liners are obtained by using HfSix/HfO2 gate stacks with Tinv=1.4 nm. High-performance n- and pFETs are achieved with Ion=1300 and 1000 muA/mum at Ioff =100 nA/mum, Vdd=1.0 V, and a gate length of 40 nm, respectively.

k

Extreme high-performance n- and pFETs are achieved as 1300 and 1000 uA/um at Ioff = 100 nA/um and Vdd = 1.0 V, respectively, by applying newly proposed booster technologies. The combination of top-cut dual-stress liners and damascene gate remarkably enhances channel stress especially for shorter gate lengths. High-Ion pFETs with compressive stress liners and embedded SiGe source/drain are performed by using ALD-TiN/HfO2 damascene gate stacks with Tinv = 1.4 nm on (100) substrates. On the other hand, nFETs with tensile stress liners are obtained by using HfSix/HfO2 damascene gate stacks with Tinv =1.4 nm.

n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

We have developed a dual metal gate CMOS technology with HfSi_x for nMOS and Ru for pMOS on HfO₂ gate dielectric. These gate stacks show high mobility (100% of universal mobility for electron, 80% for hole at high fields) down to T_inv of 1.7 nm and symmetrical low V_t equivalent to poly-Si/SiO₂. As a result, high drive currents of 780 muA/mum and 265 muA/mum at I_off = 1 nA/mum are achieved for V_dd = 1.0 V in L_g = 60 nm nMOS and pMOS, respectively We have applied the mobility enhancement technology to the Ru/HfO₂ pMOS by utilizing (110)-substrate. As a result, an excellent drive current of 400 muA/mum (151% improvement over (100)-p⁺poly-Si/SiO₂) is achieved

Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

We have experimentally shown that crystallization of HfO2 and the subsequent formation of fixed charges localized at the HfO2/SiO2 interface bring about a degradation of electron mobility. Systematic analyses of valence-band photoemission and transmission electron microscopy indicate that the oxygen transfer from the HfO2 layer to the Si substrate is promoted upon the crystallization of HfO2 and the fixed charges are generated during the process. These findings highlight the importance of controlling the crystallinity of HfO2 for realizing high performance metal gate high-κ field-effect transistors.

High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology

This work demonstrates the successful integration of 0.85nm-EOT Si<inf>0.45</inf>Ge<inf>0.55</inf>-pFETs using a gate first approach. An in-depth analysis, ranging from capacitor-level up to circuit-level is carried out, with systematic benchmarking to a conventional Si-channel reference. Outperforming the state-of-the-art Si<inf>0.55</inf>Ge<inf>0.45</inf>-pFETs, an I<inf>ON</inf> of 630µA/µm at L<inf>G_POLY</inf> = 35nm with I<inf>OFF</inf> = 100nA/µm and V<inf>DD</inf> = −1V has been achieved without any epi-S/D boosters. Significant improvements at lower V<inf>DD</inf> have also been confirmed through complex circuit simulations and validated by experimental results.

Mechanism of Carrier Mobility Degradation Induced by Crystallization of HfO2 Gate Dielectrics

a imec, Kapeldreef 75, 3001 Heverlee, Belgium b ESAT-INSYS department, Katholieke Universiteit Leuven, 3000 Leuven, Belgium c also Post-doctoral fellow of the Fund for Scientific Research-Flanders (FWO), 1000 Brussels, Belgium d also IWT-Vlaanderen, 1000 Brussels, Belgium e Sony assignee at imec, 3001 Leuven, Belgium f Currently at IBM g Universita della Calabria, Arcavacata di Rende, Italy h Panasonic assignee at imec, 3001 Leuven, Belgium

High-mobility 0.85nm-EOT Si 0.45 Ge 0.55 -pFETs: Delivering high performance at scaled VDD

We have developed a high performance pMOSFET with ALD-TiN/HfO2 gate stacks on (110) substrate using gate last process at low temperature. High work function and low gate leakage current are obtained. An extremely high mobility equivalent to P+poly-Si/SiO2 on (110) substrate (171 cm2/Vs at 0.5 MV/cm) is achieved with ALD-TiN/HfO2 on (110) substrate in the thinner Tinv region of 1.7 nm. Vth roll-off characteristics are well controlled down to 50 nm. A high drive current of 380 uA/um at I off = 1 uA/um is achieved at Vdd = 1.0 V. The drive current of ALD-TiN/HfO2 gate stack on (110) substrate is improved 1.4 times compared with (100) substrate and 2.4 times compared with P+poly-Si/SiO2 on (100) substrate

Si1-xGex-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type FinFETs and p-type Si1-xGex-channel pFETs, and relies mainly on TCAD results. It will be shown that on n-FinFETs, tensile stressed Contact EtchStop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. Tensile stressed gates are shown to be an effective stressor on gatefirst n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. For pFETs with strained Si1-xGex-channels like the Implant-Free Quantum Well (IFQW) FET, it will be shown that elastic relaxation during source/drain recess is an important factor that reduces the effectiveness of Si1-yGey source/drain stressors. For scaled technologies, omitting the source/drain recess altogether and opting for a raised source/drain scheme is preferred. In IFQW pFETs, dependence of the drive current on transistor width is an important concern. It will be shown that a Si1-yGey source/drain reduces the layout dependence of IFQW FETs, an effect that is enhanced further when combined with a gate-last integration scheme.