Shinsuke Sakashita

Diffusion Control Techniques for TiN Stacked Metal Gate Electrodes for p-Type Metal Insulator Semiconductor Field Effect Transistors

We have investigated a polycrystalline silicon (poly-Si)/chemical vapor deposited titanium nitride (CVD-TiN) stacked structure as a metal gate with a high-k for p-type metal insulator semiconductor field effect transistors (p-MISFETs). A divided-CVD method provided an appropriate effective work function (4.9–5.2 eV) on HfSiON for p-MISFETs. However, the deposition of poly-Si on CVD-TiN films shifted the effective work function to a midgap (~4.6 eV), and Ti, Hf, and Si diffused into poly-Si/CVD-TiN/high-k structures during poly-Si deposition. Then, we found that an increase in the deposition temperature of CVD-TiN films and the insertion of a physical vapor deposited (PVD)-TiN film between the poly-Si and CVD-TiN layers are effective in suppressing these diffusions. In particular, the insertion of the PVD-TiN film provided an appropriate effective work function of 4.9 eV. Therefore, we found that the diffusion control techniques for poly-Si/TiN/high-k stacked structures are highly effective for obtaining the appropriate work function for p-MISFETs.

Investigation of the divided deposition method of TiN thin films for metal-insulator-metal capacitor applications

TiCl4-based chemical vapor deposition (CVD) of TiN films was studied for the application of the top electrode of TiN/Ta2O5/TiN metal–insulator–metal (MIM) capacitors in embedded dynamic random-access memories (eDRAMs). In order to achieve a low level of capacitor leakage current, TiN-CVD at low deposition temperatures of 450°C or less was effective. At such low deposition temperatures, the resistivity of the TiN films increased rapidly as the film thickness decreased. On the other hand, the density of the anomalous growth substances on the TiN film surfaces was higher for the thicker TiN films. We clarified that these two problems were simultaneously unsolvable by means of the usual TiCl4-based TiN-CVD method. In order to avoid the appearance of these phenomena, we applied the divided TiN deposition method to the top electrode formation of the MIM capacitors. This method consists of several repetitions of the deposition step and a subsequent NH3 annealing step. The low film resistivity (~1800 µΩ cm) and the low capacitor leakage current were achieved without the anomalous growth by using the divided deposition method at 350°C. It is expected to be a promising method for the top electrode formation of MIM capacitor structures of the eDRAMs.

Phase and Composition Control of Ni Fully Silicided Gates by Nitrogen Ion Implantation and Double Ni Silicidation

The phase and composition control of a Ni fully silicided (Ni-FUSI) gate electrode is investigated to achieve a wider process window for complementary metal–oxide–semiconductor (CMOS) device integration. We performed nitrogen ion implantation (N2 I/I) on polycrystalline silicon (poly-Si) prior to Ni deposition only for an n-MOS gate. The implanted nitrogen in the poly-Si layer suppresses the reaction of Ni and Si. As a consequence, the process temperature for Ni silicidation increased by ~20 °C compared with that in the case without implantation. It was also found that the grain size of the Ni silicide found in the N2 I/I-treated poly-Si layer is smaller, possibly due to nitrogen atoms bound to Si and/or cavities generated inside the poly-Si layer. We also propose double Ni silicidation for fabricating a p-MOS gate, where a Ni-rich silicide was formed by carrying out an additional Ni deposition and annealing on a Ni silicide film. The Ni-rich silicide was evaluated in terms of X-ray diffraction patterns and flat band voltage shifts on capacitance–voltage measurement. Combining these techniques will enable the development of an optimized process integration scheme for CMOS devices.

Enhanced Performance of Gate-First p-Channel Metal-Insulator-Semiconductor Field-Effect Transistors with Polycrystalline Silicon/TiN/HfSiON Stacks Fabricated by Physical Vapor Deposition Based In situ Method

We demonstrated the use of an in situ metal/high-k fabrication method for improving the performance of metal–insulator–semiconductor field-effect transistors (MISFETs). Gate-first pMISFETs with polycrystalline silicon (poly-Si)/TiN/HfSiON stacks were fabricated by techniques based on low-damage physical vapor deposition, in which high-quality HfSiON dielectrics were formed by the interface reaction between an ultrathin metal-Hf layer (0.5 nm thick) and a SiO2 underlayer, and TiN electrodes were continuously deposited on the gate dielectrics without exposure to air. Gate-first pMISFETs with high carrier mobility and a low threshold voltage (Vth) were realized by reducing the carbon impurity in the gate stacks and improving the Vth stability against thermal treatment. As a result, we obtained superior current drivability (Ion = 350 µA/µm at Ioff = 200 pA/µm), which corresponds to a 13% improvement over that of conventional chemical vapor deposition-based metal/high-k devices.

Performance Enhancement in 45-nm Ni Fully-Silicided Gate/High-k CMIS Using Substrate Ion Implantation

High performance Ni-FUSI/HfSiON CMIS with suitable Vth in a wide Lg range is presented. This is accomplished by ion implantation to substrate and phase control of Ni-FUSI gate. Threshold voltage of NiSi-FUSI NMIS is controlled by nitrogen implantation, and that of Ni2Si-FUSI PMIS is controlled by fluorine implantation. It is demonstrated that N/F incorporation can realize 0.2-V-low |Vth|, high carrier mobility, and high reliability for both NMIS and PMIS. Drain current increases by 16% for NMIS and by 55% for PMIS compared with poly-Si/high-k CMIS. Substrate ion implantation engineering is promising for multi-Vth CMIS platform for 45-nm node and beyond

Cost Worthy and High Performance LSTP CMIS; Poly-Si/HfSiON nMIS and Poly-Si/TiN/HfSiON pMIS

High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability. It is demonstrated that this cost-worthy process provides performance which is competitive to reported dual metal CMOS

Advanced Poly-Si NMIS and Poly-Si/TiN PMIS Hybrid-Gate High-k CMIS using PVD/CVD-Stacked TiN and Local Strain Technique

Performance of advanced hybrid-gate CMOS (poly-Si/HfSiON nMIS and poly-Si/TiN/HfSiON pMIS) is demonstrated. Vth of pMIS is controlled by fluorine implantation and by PVD/CVD-stacked TiN, which has higher WF than conventional single-CVD TiN. This combination enables sufficient Vth-control without degradation of device characteristics by excessive fluorine. Performance boosters such as strain enhancement techniques and laser annealing are easily and successfully introduced, and high current drivability is obtained. This advanced hybrid structure is promising for CMIS platforms of 45-nm node and beyond.

High Performance Gate-First pMISFET with TiN/HfSiON Gate Stacks Fabricated with PVD-Based In-Situ Method

Fermi-level pinning on Hf-based high-k with poly-Si, resulting in high and uncontrollable threshold voltage (Vth) especially in pMIS, has been a serious concern. Therefore, cost-worthy and high-performance LSTP cMISFETs with poly-Si/HfSiON nMIS and polySi/TiN/HfSiON pMIS have been studied [1,2]. In these references, HfSiON and TiN films were formed by CVD methods, respectively [3,4], and these films include some impurities such as Cl and C from CVD sources and air. It has already been reported that the residual impurities in the high-k gate stack degraded the device performance [5]. Then, PVD-based in-situ method for TiN/HfSiON stack is much attractive because it can minimize the impurities both within HfSiON layer and metal/high-k interface. This method is as follows; PVD-grown metalHf layer on SiO2 underlayer was fully consumed by annealing of solid phase interface reaction (SPIR) to form Hf-silicate [6], and TiN film was continuously grown on the Hf-silicate with low-damage PVD without exposure to air [7]. In this work, we investigated the effects of this PVD-based in-situ method on the pMISFET properties, comparing with the usual ex-situ CVD methods. P-doped poly-Si films were grown on these TiN /HfSiON stacks by an ex-situ CVD. MISFETs were fabricated by a conventional gate-first process that includes gate dry etching and spike-RTA up to 1050oC. Vg-Id&Ig curves and Vth roll-off characteristics of polySi/TiN/HfSiON stacks fabricated by different 3 processes, 1) ex-situ CVD-TiN on CVD-HfSiON, 2) ex-situ PVDTiN on CVD-HfSiON, and 3) in-situ PVD-TiN on SPIRHfSiON, were shown in Figs. 1 and 2. These indicate that the suitable subthreshold swing (S) of 1) 65.0, 2) 66.4, and 3) 65.5 mV/dec could be obtained, and that the Vthvalues were 1) -0.64, 2) -0.46, and 3) -0.44V at Lg=10μm, respectively. PVD-TiN could provide relatively low Vth, probably because PVD-TiN had less impurity and better film quality than CVD-TiN, and it could restrain the diffusion of Si from poly-Si to high-k [4]. SPIR-HfSiON and in-situ process could reduce Vth more, probably due to the reduction of C impurity both within HfSiON layer and metal/high-k interface. On the other hand, fluorine ion implantation into the substrate has been reported that it was an attractive method for controlling Vth in pMIS [3]. Figure 3 shows the comparison of Ion-Ioff characteristics between different 3 processes, a) ex-situ CVD-TiN on CVD-HfSiON, b) exsitu CVD-TiN on CVD-HfSiON with substrate fluorine ion implantation, and c) in-situ PVD-TiN on SPIRHfSiON. As the amount of F implantation increases, Vth is reduced, however, when too much F was implanted, IonIoff characteristics deteriorated as shown in Fig. 3. This is probably due to the deterioration of S-value [8]. The PVD-based in-situ method could provide Ion=350μA/μm at Ioff=200pA/μm, which was a 15% improvement over ex-situ CVD-TiN on CVD-HfSiON. Other superior pMISFET properties, such as Vth, S-value, hole mobility, and gate leakage current, could also be obtained, because this in-situ method could minimize the impurities. Moreover, this PVD-based in-situ method with moderate F implantation would reduce Vth even more without deterioration of Ion.

Reduction of Threshold Voltage by Diffusion Control Technique in p-MISFETs Using Poly-Si/TiN/HfSiON Gate Stacks

The effects of the diffusion control technique by inserting physical vapor deposition (PVD)-TiN film between poly-Si and CVD-TiN films on the properties of p-MISFETs using poly-Si/TiN/HfSiON gate stacks have been studied. This insertion was effective in suppressing the diffusion of Si from poly-Si to HfSiON and was able to reduce the Vth value by 0.12 V while keeping the equivalent oxide thickness and S value constant, when the thicknesses of the PVD and CVD-TiN films were 10 and 5 nm, respectively. Although too much ion implantation of fluorine into the substrate deteriorates S value and ION, it was verified that this diffusion control technique, in conjunction with a moderate substrate fluorine implantation, provided a reduction of Vth in pMIS without a deterioration of ION.

Low temperature divided CVD technique for TiN metal gate electrodes of p-MISFETs

Shinsuke Sakashita, Kenichi Mori, Kazuki Tanaka*, Masaharu Mizutani, Masao Inoue, Shinichi Yamanari, Jiro Yugami, Hiroshi Miyatake, and Masahiro Yoneda Process Development Dept., Process Technology Development Div., Production and Technology Unit, Renesas Technology Corporation *Process Engineering Section, Wafer Process Engineering Dept., Renesas Semiconductor Engineering Corporation 4-1, Mizuhara, Itami-shi, Hyogo, 664-0005, Japan Phone: +81-72-784-7373 / Fax: +81-72-780-2756 / E-mail: sakashita.shinsuke@renesas.com