Jiro Yugami

Fluorine incorporation into HfSiON dielectric for V/sub th/ control and its impact on reliability for poly-Si gate pFET

F incorporation into HfSiON dielectric using channel implantation technique is shown to be highly effective in lowering Vth and improving NBTI in poly-Si gate pFET. Mobility degradation is not accompanied and drive current is increased by 180%. From analytical and electrical characterization, the Vth shift is attributed to change in trap density

Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics

Negative bias temperature instability (NBTI) of pMOSFETs with direct-tunneling SiON gate dielectrics was studied in detail. By investigating the effects of applying positive gate bias on pMOSFETs after exposure to NBT stress, the generation of bulk charge traps in the gate dielectrics during NBTI was clearly demonstrated. In particular, it was found that a positive charge generated by negative bias temperature stress (NBT stress) can be neutralized and that the neutralized site can return to the positive state. We consider that the bulk trap is due to hydrogen atoms released from the interface between the SiON gate dielectric and the Si substrate (and this is what has conventionally been considered a positive fixed charge). Moreover, the bulk trap generation was shown to give rise to stress-induced leakage current.

Two concerns about NBTI issue: gate dielectric scaling and increasing gate current

In order to obtain a clear perspective concerning the negative bias temperature instability (NBTI) issue toward 65-nm-node and beyond, (1) the impact of thinning gate dielectric on the basic mechanism of NBTI and (2) the influence of gate electron current on NBTI degradation rate have been investigated. Both were studied with focus on the hydrogen release reaction. This is believed to be the origin of NBTI. By studying the diffusion behavior of released hydrogen, we have clarified that our experimental results of NBTI degradation obtained under voltage-accelerated conditions can be explained by the widely accepted diffusion-controlled model without taking the influence of the gate electrode interface into account even in the case of sub-nm SiON gate dielectrics. However, from numerical calculations, it has been shown that the effect of the gate electrode interface on the diffusion behavior of released hydrogen should be taken care of at stress voltage as low as that of practical operation. In particular, the possibility of NBTI worsening due to thinning gate dielectric has been suggested especially for low stress voltage. To foresee this NBTI worsening and to evaluate NBTI lifetime precisely, we have proposed temperature-acceleration test instead of voltage-acceleration test. Next, by studying NBTI of n+gate-pMOSFET in which the influence of gate electron current is dramatically emphasized, it has been examined whether electron current flowing through gate dielectric will affect NBTI or not. Although the primary driving force of NBTI is considered to be the electric field, electron tunneling current that flows under NBT stress has been shown to worsen NBTI via the suppression of the reverse reaction of hydrogen release.

Positive charge generation due to species of hydrogen during NBTI phenomenon in pMOSFETs with ultra-thin SiON gate dielectrics

Negative bias temperature instability (NBTI) of pMOSFETs with ultra-thin SiON gate dielectrics was investigated. We focused our attention on the behavior of hydrogen atoms released from the interface under NBT stress. From the transient characteristics of pMOSFETs after NBT stresses were stopped, it was found that a portion (60%, in our case) of hydrogen atoms released by the NBT stress remain in a 1.85-nm-thick NO-oxynitride gate dielectric. The existence of the hydrogen in the gate dielectric was shown to lead to the generation of positive charges.

Tunneling acoustic microscope

A tunneling acoustic microscope is a new type of microscope which is based on both a scanning tunneling microscope and a technique for detecting acoustic waves. It enables simultaneous detection of force interactions between tip and sample and tunneling current. Using this new microscope, defects on silicon surface induced by thermal oxidation have been observed by detecting changes in surface conductivity with high spatial resolutions.

Advantages of gate work-function engineering by incorporating sub-monolayer Hf at SiON/poly-Si interface in low-power CMOS

The impact of gate work-function (WF) engineering on low-power devices is investigated by incorporating sub-monolayer Hf at SiON/poly-Si interface. An increase of threshold voltage (V/sub T/) by WF control allows the use of lower substrate impurity concentrations. This leads to significant increase of carrier mobility and thus I/sub ON/. Moreover, the gate leakage current is reduced by WF control due to the decrease of oxide field or the increase of barrier height. We successfully demonstrate improvement of 16 % (nFET) and 5 % (pFET) in I/sub ON/ for 65-nm LOP devices when V/sub dd/ = 0.9 V.

A simple approach to optimizing ultra-thin SiON gate dielectrics independently for n- and p-MOSFETs

A technique for optimizing ultra-thin (EOT ~ 1.1-1.3 nm) SiON gate dielectrics independently for n- and p-MOSFETs is demonstrated. Selective nitrogen-enrichment for the nMOS and fluorine incorporation to the pMOS regions were both performed by ion implantation into the Si-substrate with resist masks before gate oxidation. The former provided suppression of gate leakage current and enhancement of drain current to nMOSFETs. The latter improved the NBTI of pMOSFETs without enhancing the B penetration. Moreover, the incorporation of F was found to be a quite useful tool for lowering |Vth| in pMOSFETs. The incorporation of F was shown to bring down pMOS |Vth| by more than 150 mV without any degradation in hole mobility or short channel effect immunity. Since pMOSFETs with N-rich SiON gate dielectrics, as well as high-k pMOS, suffer from excessively high |Vth|, this finding is quite important. In fact, by applying the F-incorporation technique to 65-nm devices, significant Ion enhancement (~8%) was successfully achieved for high Ioff conditions. This technique is considered operative also for pMOSFETs with high-k gate dielectrics and/or metal gate electrodes

Vth-tunable CMIS platform with high-k gate dielectrics and variability effect for 45nm node

A simple high-k/poly-Si dual-gate CMIS platform with a novel method to control threshold voltage (Vth) has been proposed for 45nm node. The PMIS Vth control method is a simple selective fluorine-implantation to channel region with optimizing extension and pocket implantation. We have also demonstrated the transistor variability improvement with our HfSiON/poly-Si platform, compared to SiON/poly-Si platform by practical fully-operating 90nm-node 8Mb-SRAMs

Stress from Discontinuous SiN Liner for Fully Silicided Gate Process

New materials often force modification in a metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process and a device structure. In our investigation, a high-stress silicon nitride (SiN) contact etch stopper layer (CESL), which improves device performance by straining the Si lattice, was used as the modified structure. A portion of its gate surround was cut to fabricate a fully silicided (FUSI) metal gate. FET characteristics of a polycrystalline silicon (poly-Si) gate and a Ni-FUSI gate MOSFET with a discontinuous CESL were compared with those of a poly-Si gate MOSFET with an ordinary continuous CESL for several SiN-stress conditions. It was found that the removal of a gate-top CESL diminishes mobility modulation effects of a high-stress CESL. It was also demonstrated that stress due to a FUSI gate compensates the effect of gate-top CESL removal. Mobility enhancement utilizing a high-stress SiN film was still effective for a FUSI gate process.

Phase and Composition Control of Ni Fully Silicided Gates by Nitrogen Ion Implantation and Double Ni Silicidation

The phase and composition control of a Ni fully silicided (Ni-FUSI) gate electrode is investigated to achieve a wider process window for complementary metal–oxide–semiconductor (CMOS) device integration. We performed nitrogen ion implantation (N2 I/I) on polycrystalline silicon (poly-Si) prior to Ni deposition only for an n-MOS gate. The implanted nitrogen in the poly-Si layer suppresses the reaction of Ni and Si. As a consequence, the process temperature for Ni silicidation increased by ~20 °C compared with that in the case without implantation. It was also found that the grain size of the Ni silicide found in the N2 I/I-treated poly-Si layer is smaller, possibly due to nitrogen atoms bound to Si and/or cavities generated inside the poly-Si layer. We also propose double Ni silicidation for fabricating a p-MOS gate, where a Ni-rich silicide was formed by carrying out an additional Ni deposition and annealing on a Ni silicide film. The Ni-rich silicide was evaluated in terms of X-ray diffraction patterns and flat band voltage shifts on capacitance–voltage measurement. Combining these techniques will enable the development of an optimized process integration scheme for CMOS devices.