Shinya Ohba

MOS area sensor: Part II—Low-noise MOS area sensor with antiblooming photodiodes

The development of a high-sensitivity 320 × 244 element MOS area sensor and a novel fixed pattern noise (FPN) suppressing circuit are reported in this paper. The new device incorporates p+-n+high-C photodiodes and double-diffused sense lines. The p+-n+high-Cphotodiodes provide a large dynamic range and a large saturation signal of 1.4 µA with 6-1x W-lamp illumination. The double-diffused sense lines are introduced to vastly improve blooming characteristics, making use of a built-in potential barrier. FPN is proved to stem mainly from inversion charge variations through horizontal switching MOS gate capacitances. A simple high-performance FPN suppressing circuit is proposed which realizes high signal-to-noise (S/N) ratios of more than 68 dB at saturation. The new sensor is tested in a high-sensitivity black-and-white VTR hand-held camera and will find broad applications.

Design consideration and performance of a new MOS imaging device

The design considerations and performance of a new MOS imaging device with novel random noise suppression (RANS) circuits are described. This device consists of 492 × 388 photodiodes, a vertical shift register, and a horizontal BCD register integrated in p-wells. The RANS circuits accelerate the charge-transfer speed from vertical signal lines to a horizontal BCD register with 98-percent efficiency. They also decrease the effective signal line capacitance, so noise due to the transfer MOS switches is suppressed to obtain a high signal-to-noise ratio of 46 dB at a standard scene illumination of 180 lx (F1.4) with no image lag and blooming. Sweep out operation for the smear charge accumulated in the vertical signal lines realizes a sufficient signal-to-smear ratio of 69 dB at 1/10 vertical scene illumination.

2/3-inch format MOS single-chip color imager

A new 2/3 format MOS single-chip color imager, that includes 384 × 485 elements, has been developed. The device features a low-noise design; high sensitivity (9 nApp/lx for 2855 K W lamp), through employment of a complementary color filter; and wide dynamic range (over 60 dB), through introduction of a p+-layer in the photodiode and a vertical buffer circuit. The imager also features low aliasing (Moire) and clear color due to the use of a new color filter arrangement and unique multivideo lines. The die measures 10.0mm × 8.5 mm, which is realized using standard 3-µm Si-gate MOSLSI technology. Combining this small size and technological simplicity with on-wafer color filter processing, has made this device suitable for LSI volume production.

A 20-ns CMOS micro DSP core for video-signal processing

A programmable 8-b digital signal processor core with an instruction cycle time of 20 ns is developed. A 37.5-mm chip is fabricated by advanced 1.0- mu m double-level-metal CMOS technology. This processor has a reconfigurable high-speed data path supporting several multiply/accumulate function, including 16-tap linear-phase transversal filtering, high-speed adaptive filtering, and eight-point discrete cosine transformation. To provide high-speed operation within the chip, a programmable phase-locked loop circuit is built on the chip. This circuit generates a high-speed clock, which is a multiple of the system clock fed from outside, and is synchronized to the system clock. >

MOS imaging with random noise suppression

This paper will describe an MOS imaging device that integrates a random noise suppression circuit which realizes a signal-to-noise ratio of 46dB at a scene illumination of 180 l (F 1.4) and smear noise of 69dB with no image lag.

A 1/2-in CCD imager with lateral overflow-gate shutter

The design considerations and performance of an interline-transfer charge-coupled-device (IL-CCD) imager with a lateral overflow gate shutter are described. A 489(V)-pixel*670(H)-pixel 1/2-in IL-CCD imager is shown to have a variable shutter function, whose shutter speed is controlled successively from 1/60 to 1/15700 s by the timing of the overflow gate pulse. The device requires a low voltage of only 4 V and a simple overflow gate pulse to realize the shutter function without any undesirable die size enlargement. The key technology of the device is the self-aligned photodiode structure, which realizes a complete charge transfer. Combined with a microlens on the photodiode, the device can achieve high-definition or small-die-size imagers because of its high sensitivity. >

New solid-state image pickup devices using photosensitive chalcogenide glass film

A new solid-state imager, in which the photosensitive Se-As-Te chalcogenide layer is separated from and deposited on the Si scanning array, has been fabricated and successfully operated. The n-MOS FET array used as a scanner has 320(H) × 244 (V) scanning elements and each element measures 27 µm by 27 µm. New processes such as the heat treatment of the photoconductive film during its evaporation, and the low temperature deposition of a transparent electrode, have made it possible to obtain defect-free imaging devices. Applying a target voltage of 40 V to the transparent electrode, we have obtained high sensitivity over the whole visible region. A blue(450 nm) sensitivity of 0.2 µA/µW obtained with this sensor is comparable to the tube sensitivity using the same target film. An SN ratio greater than 40 dB has been realized. Without any special antiblooming control, blooming phenomenon has been suppressed up to the scene illumination over 20 Klx(f4).

2/3-Inch Format MOS Single-Chip Color Imager

A new 2/3-in format MOS single-chip color imager, that includes 384 X 485 elements, has been developed. The device features a low-noise design; high sensitivity (9 nApp/lx for 2855 K W lamp), through employment of a complementary color filter; and wide dynamic range (over 60 dB), through introduction of a p/sup +/-layer in the photodiode and a vertical buffer circuit. The imager also features low aliasing (Moire) and clear color due to the use of a new color filter arrangement and unique multivideo lines. The die measures 10.0 mm X 8.5 mm, which is realized using standard 3-/spl mu/m Si-gate MOSLSI technology. Combining this small size and technological simplicity with on-wafer color filter processing, has made this device suitable for LSI volume production.

Vertical smear noise model for MOS-type color imager

The smear noise in an MOS imager was analyzed based on the three types of generation mechanisms: capacitive coupling, carrier diffusion, and light leakage. The measured smear performance was explained by these analyses. The results lead to the conclusion that the main cause of smear in an MOS imager is due to the component of light leakage.

A wideband low-noise analog delay line

A 128-bit color signal delay line for commercial TV, successfully operated by introducing a self-aligned electrode and an integrated low-noise analog sample holder to buried-channel charge-transfer devices, will be discussed.