Shiqiang Qin

Unipolar

In this letter, a reproducible unipolar resistive change memory (RRAM) based on TaOx was successfully fabricated through electrode design. The fabricated unipolar RRAM exhibits lower switching voltages, fast switching speed of less than 80 ns, excellent retention capabilities, and stable cycling behaviors. Moreover, the role of top-electrode material on the resistive switching mode polarity of TaOx-based RRAM was verified by comparative experiments. Analysis about the electrode effect on the resistive switching mode polarity of TaOx-based RRAM with the theory of Gibbs free energy may provide some guidelines for the design of unipolar metal-oxide-based RRAM.

\hbox{TaO}_{x}

In this paper, a tunneling filed effect transistor (TFET) based flash memory with high-gate injection efficiency is proposed and experimentally demonstrated. The measured injection efficiency (gate current (Ig) / drain current (Id)) during programming is more than 10-4 in TFET flash devices which is two orders higher than that of the conventional ones. It is considered that this high injection efficiency is attributed to the strong channel electric field near source region. The results imply that this TFET flash device is promising for low power operation.

-Based Resistive Change Memory Realized With Electrode Engineering

In this paper, a high thermal stable TaOx-based RRAM device has been fabricated with TiN as the top electrode. The fabricated device shows good endurance behavior with little fluctuations in voltages and resistance state. Due to the stability of this device, potential for MLC application was also investigated. In addition, the mechanism of the high performance of the device is analyzed with Gibbs free energy based on the TEM-analysis and comparative experiments.

High-gate-injection tunneling field effect transistor for flash memory applications

A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is proposed and investigated in this paper. Based on the TFET structure, the proposed novel flash memory cell shows high programming efficiency, low power consumption, and good punch-through immunity. Unlike traditional NOR Flash cell which adopts the channel hot carrier (CHE) injection near drain side for programming operation, the TFET flash memory cell utilizes hot electrons injection introduced by band-to-band tunneling near source side for programming, which can achieve 3 orders higher programming efficiency due to greatly alleviated competition between the vertical electric field and lateral electric field. Moreover, the programming leakage current is 2 orders lower due to the high punch-through immunity for TFET structure. The obtained results and theoretical analysis demonstrate that the newly proposed flash cell can be a potential candidate for low power, and high density NOR-type flash applications.

Thermally stable TaO x -based resistive memory with TiN electrode for MLC application

A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is investigated via 2-D device simulation in this paper. The proposed flash memory cell shows improved program/erase speed, increased programming efficiency and super punch-through immunity as the cell gate length scaled from 180nm to 45nm, which indicates that this new structure is with strong scalability. Furthermore, cell design consideration i.e. ambipolar suppression for the TFET-based flash cell are also investigated and discussed.

A Novel High Programming Efficiency and Highly Scalable Flash Memory Cell Based on Tunneling FET (TFET)

We investigated source potential impacts on drain disturb of NOR Flash cells and proposed a novel source-biased measurement which can separate channel leakage current disturb and band-to-band disturb. By this method we explored the origins of drain disturb of Nanoscale Flash Memory. Our results indicate that, under channel ionized secondary electron (CHISEL) injection operation, drain disturb originates from both drain side band-to-band tunneling (∼0.66 V) and source-drain leakage (∼0.4 V) when NOR Flash scales into 65 nm, which means to suppress drain disturb it is important to decrease source-drain leakage as well as drain junction leakage during nanoscale Flash cell design.

A novel flash memory cell and design optimization for high density and low power application

A novel polymer (organic) resistive memory device with the structure of W/parylene+Au/Al is presented in this paper. The organic memory device exhibits not only high scalability but also good compatibility with CMOS back-end process, for parylene is immune to the lithographic solvents. Moreover, parylene film could be fabricated by chemical vapor deposition (CVD) instead of spin-coating, thus the quality and uniformity of the film can be improved. The device exhibits good nonvolatile memory characteristics, including low operating voltage (1.5 V / −3 V) and good retention capability (29000 s). A possible switching mechanism is also proposed and supported by the experimental data. The device shows great potentials for flexible, stackable and high-density memory applications.