Poren Tang

Total Ionizing Dose (TID) Effects on

In this brief, the total ionizing dose (TID) effects of γ rays generated from a 60Co source on the TaOx-based resistive switching memory (resistive random-access memory, RRAM) is investigated. The low-resistance state (LRS) of the RRAM is immune to TID effects, whereas the sensitivity of the high-resistance state (HRS) of RRAM to TID effects depends on the dimensions of the device, including the thickness of the oxide film and the area of the device. The HRS of the device with large area and thick oxide layer is vulnerable to TID effects and has a high probability to change into the LRS. Further investigation found that the lower the high resistance, the higher the failure rate of the RRAM device under TID impact, which indicates that the multilevel cell of RRAM should be carefully designed for space system applications considering the radiation effects. The failure of the HRS under TID is explained by defect generation in the oxide film.

\hbox{TaO}_{x}

In this letter, a reliable nonvolatile resistive switching device based on silicon monoxide (SiO) is demonstrated. The device was fabricated with a low-temperature process that can be compatible with a CMOS back-end process and attractive for 3-D memory integration. The fabricated Cu/SiO/W device was found to have a repeatable unipolar resistive switching behavior. The results show excellent on/off resistance ratio (over 104) and good retention performance. The switching mechanism of the device is analyzed by experimental data and probably can be attributed to the behaviors of copper ions in the bulk of SiO under different voltages.

-Based Resistance Change Memory

A novel band-gap engineered source and drain floating body cell (BESD-FBC) for capacitorless dynamic random access memory (DRAM) Cell is proposed and investigated for the first time. The energy band offset with silicon–carbon source and drain can help to form a deeper potential well in the body region, which can effectively store more holes. Compared with normal FBC, BESD-FBC can obtain larger sensing margin and longer retention time due to more stored holes and small hole leakage current. These improvements show that the proposed BESD-FBC has great potentials for future high density capacitorless DRAM application.

Unipolar Resistive Switch Based on Silicon Monoxide Realized by CMOS Technology

A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is proposed and investigated in this paper. Based on the TFET structure, the proposed novel flash memory cell shows high programming efficiency, low power consumption, and good punch-through immunity. Unlike traditional NOR Flash cell which adopts the channel hot carrier (CHE) injection near drain side for programming operation, the TFET flash memory cell utilizes hot electrons injection introduced by band-to-band tunneling near source side for programming, which can achieve 3 orders higher programming efficiency due to greatly alleviated competition between the vertical electric field and lateral electric field. Moreover, the programming leakage current is 2 orders lower due to the high punch-through immunity for TFET structure. The obtained results and theoretical analysis demonstrate that the newly proposed flash cell can be a potential candidate for low power, and high density NOR-type flash applications.

Performance Improvement of Capacitorless Dynamic Random Access Memory Cell with Band-Gap Engineered Source and Drain

A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is investigated via 2-D device simulation in this paper. The proposed flash memory cell shows improved program/erase speed, increased programming efficiency and super punch-through immunity as the cell gate length scaled from 180nm to 45nm, which indicates that this new structure is with strong scalability. Furthermore, cell design consideration i.e. ambipolar suppression for the TFET-based flash cell are also investigated and discussed.

A Novel High Programming Efficiency and Highly Scalable Flash Memory Cell Based on Tunneling FET (TFET)

We investigated source potential impacts on drain disturb of NOR Flash cells and proposed a novel source-biased measurement which can separate channel leakage current disturb and band-to-band disturb. By this method we explored the origins of drain disturb of Nanoscale Flash Memory. Our results indicate that, under channel ionized secondary electron (CHISEL) injection operation, drain disturb originates from both drain side band-to-band tunneling (∼0.66 V) and source-drain leakage (∼0.4 V) when NOR Flash scales into 65 nm, which means to suppress drain disturb it is important to decrease source-drain leakage as well as drain junction leakage during nanoscale Flash cell design.

A novel flash memory cell and design optimization for high density and low power application

A novel quasi-silicon-on-insulator (quasi-SOI) flash memory cell is proposed for the first time. By utilizing quasi-SOI structure, program/erase (P/E) performance improvement is achieved due to the enhancement of electric field in the injection region, compared with conventional cell structure. Moreover, the off-state current at large drain bias is greatly reduced by 2 orders of magnitude with the help of the L-shaped dielectric layer, indicating better program-failure immunity and lower unexpected power consumption. With punch-through effect alleviated, the novel flash cells have better scalability. Through the results and analysis, the proposed flash cell can be a potential candidate for NOR-type applications.

Investigation of source potential impacts on drain disturb in Nanoscale Flash Memory

In this paper, a low-voltage recessed channel SONOS flash memory using the gate-injection program/erase method is proposed and investigated for NAND application. It is shown that the proposed flash memory can achieve 8 V lower programming voltage compared with planar flash memory, due to the effective capacitance coupling and the electric-field enhancement by combining the recessed channel structure and the gate-injection program/erase method. In addition, more than 30% larger threshold voltage window and improved short channel effects can be obtained in the proposed flash memory.

Performance improvement of flash memory with a novel quasi-SOI structure

A novel polymer (organic) resistive memory device with the structure of W/parylene+Au/Al is presented in this paper. The organic memory device exhibits not only high scalability but also good compatibility with CMOS back-end process, for parylene is immune to the lithographic solvents. Moreover, parylene film could be fabricated by chemical vapor deposition (CVD) instead of spin-coating, thus the quality and uniformity of the film can be improved. The device exhibits good nonvolatile memory characteristics, including low operating voltage (1.5 V / −3 V) and good retention capability (29000 s). A possible switching mechanism is also proposed and supported by the experimental data. The device shows great potentials for flexible, stackable and high-density memory applications.

A low-voltage flash memory cell utilizing the gate-injection program/erase method with a recessed channel structure

In this paper, a novel single-poly electrically erasable programmable read-only memory (EEPROM) using a metal finger coupling capacitor is proposed and fabricated with a pure logic CMOS process. The metal interconnect layer is applied to form the finger-type capacitor which can be used as the coupling capacitor in the EEPROM cell. Using the metal finger capacitor, the proposed cell exhibits the advantages of a metallic control gate and features a higher coupling ratio to achieve smaller cell area and lower program/erase voltage. The program/erase characteristics, endurance and retention performances are presented. In addition, the EEPROM cell with a stacked metal finger structure can further improve the coupling ratio. Thus, lower operation voltage can be obtained without increasing the cell area.