Shojiro Mori

Essential issues for IP reuse

With widespread recent emphasis on System-On-a-Chip (SOC), IP reuse has emerged as a vital and growing business in semiconductor industry. In this paper, we will address essential issues for IP reuse by discussing current challenges to the success of IP businesses and identifying the obstacles that need to be overcome.

Embedded tutorial: essential issues for IP reuse

With widespread recent emphasis on System-Ona-Chip (SOC), IP reuse has emerged as a vital and growing business in semiconductor industry. In this paper, we will address essential issues for IP reuse by discussing current challenges to the success of IP businesses and identifying the obstacles that need to be overcome.

A Compaction Method for Full Chip VLSI Layouts

An algorithm independent layout compaction method for full chip layouts is proposed. The partitioning compaction method cuts up a large layout, compacts each block independently and then merges them to give the final compacted layout. A 16-bit CPU core (28.8K transistors) layout was compacted on a standard workstation using this method. Both the computer memory usage and processing time were reduced. Parallel processing is possible to further speed up the computation.

Hierarchical symbolic design methodology for large-scale data paths

A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21 K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design. >

Datapath generator based on gate-level symbolic layout

This paper describes a new datapath generator that generates high-density mask layouts equivalent to hand-crafted ones. An entry of the generator is a hierarchical symbolic layout at the gate level. <italic>Bit-and-row-slicing technique</italic> is a key feature to realize large-size and high-density datapath generation. A 21K transistor datapath was generated using 1-μm CMOS technology, whose density is 5.64 KTr/mm<supscrpt>2</supscrpt>, greater than the 5.38 KTr/mm<supscrpt>2</supscrpt> of a hand-crafted datapath.

Symbolic design methodology for high-density macro-cell

A design methodology is proposed for macro-cell design. Macro-cell layout is optimized at symbolic design level. So-called versatile cells are used to make the best use of symbolic layout features. Unnecessary jogs are eliminated by fitting versatile cells into surrounding circuits. If a macro cell is composed of small circuit components, eliminating jogs greatly reduces circuit component connecting area. The stick-diagram-generating system KIMERA was implemented to realize the methodology.<<ETX>>

Hierarchical symbolic design methodology for large-scale datapaths

A hierarchical symbolic layout methodology for designing large-scale datapaths is proposed. The methodology constructs a datapath hierarchically by taking note of the bit-slice regular structure. It gives a globally optimized layout with a rapid optimizing loop. This approach has reduced design effort to 1/10 compared with conventional handcraft design (maintaining equivalent layout quality) for a datapath which includes 21 K transistors. Macrocells without bit-sliced structure are also considered to be easily embedded into the final datapath layout. Moreover, as a design entry, an LT-diagram entry is allowed for a designer. The diagram is a special logic diagram which includes topological information for gates and wirings. A stick-diagram is automatically synthesized from the LT-diagram and mask layout is generated through compaction.<<ETX>>