Shuai Jin

Optimization of the transition from connector to PCB board

A transition from vertically launched coaxial connector to routed trace on board is simulated and optimized to achieve very small reflections for precise TRL calibration. The mismatch of the discontinuities in the transition was reduced by controlling the via-impedance, introducing capacitive via-pads and applying diving boards. Each segment was optimized first, and then the whole cascaded structure was simulated to achieve the optimized smooth signal transition.

Conducted-emission modeling for a switched-mode power supply (SMPS)

This paper is focused on the construction of a conducted-emission model for a switched-mode power supply (SMPS). First, the total voltage source is extracted by measurement. Second, the coupling path between the aggressor and the victim is characterized by both simulation and measurement. Finally, the coupled noise to the victim with respect to the extracted total voltage source can be obtained by both simulation and calculation. Both results match well with the measurement result, which validates the robustness of the constructed model.

Analytical and numerical sensitivity analyses of fixtures de-embedding

De-embedding procedures are sensitive to manufacturing variations in test fixtures, as well as inaccuracies associated with the calibration and measurement process. Such sensitivities can propagate through de-embedding procedures, resulting in amplified errors. In this paper, analytical and numerical techniques are used to perform sensitivity studies on both simulation and measurement data, with respect to de-embedding.

Variability analysis of crosstalk among pairs of differential vias using polynomial-chaos and design of experiments methods

The variability of the worst-case crosstalk among differential vias in response to the change of the relative locations of the ground and the differential vias are studied in this work. The polynomial-chaos (PC) and the design of experiments (DoE) methods are applied to construct the statistical models. Both methods work well. But the DoE method is preferred in our case since it takes fewer simulations.

Analytical equivalent circuit modeling for multiple core vias in a high-speed package

Core vias found in the packages of high-speed ICs can have a large impact on overall channel performance. Thus accurately modeling core vias in the package is essential. In this paper analytical methodologies are used to calculate equivalent circuit models of core vias.

Validating the transmission-line based material property extraction procedure including surface roughness for multilayer PCBs using simulations

Accurate frequency-dependent dielectric properties are important for accurate modeling of signal and power integrity problems. One method for extracting dielectric properties from fabricated multilayer printed circuit boards is based on the measured electrical property of fabricated transmission lines, denoted the “Root-omega” method. In this paper, the “Root-omega” method applied to the cases with smooth and rough conductors is validated using simulations. Potential errors in the procedure are discussed.

Conducted-Emission Modeling for a High-Speed ECL Clock Buffer

Total voltage sources and Thevenin equivalent circuits are derived by measurements and simulations using IBIS models to characterize the conducted emissions from ICs. The constructed noise source model for a test IC is applied in system-level simulations and the calculated far field radiation is validated with measurements. The agreement between simulated and measured results demonstrates the effectiveness of the constructed model for characterizing the conducted emissions from an ICs I/O pins.

Differential integrated crosstalk noise (ICN) reduction among multiple differential BGA and Via pairs by using design of experiments (DoE) method

The integrated crosstalk noise (ICN) has been wildly used as an alternative to the insertion crosstalk ratio (ICR) for channel crosstalk evaluation in the IEEE 802.3ba standard. In this work, a differential ICN analysis is performed for several configurations of package-to-PCB transitions. Using the design of experiment (DoE) statistical method, differential ICN is quickly estimated for various input factors such as pin mapping, physical dimensions, and level of shielding. Optimization guide line is proposed to maintain the tradeoff among the differential ICN, design space, and manufacturing cost.

Improved “Root-Omega” Method for Transmission-Line-Based Material Property Extraction for Multilayer PCBs

Electrical properties of dielectric substrate are critical in designing high-speed products in terms of signal and power integrity. It is important to accurately characterize the dielectric properties to avoid overestimating or underestimating in the design. This paper proposes the improved “Root-Omega” method for extracting dielectric properties from fabricated multilayer printed circuit boards. Based on the electrical properties of fabricated transmission lines, the improved “Root-Omega” method applied to cases with smooth and rough conductors is validated using simulations. Error sensitivity analysis is performed to demonstrate the potential errors in the original “Root-Omega” procedure and the error sensitivity is significantly reduced by the proposed improvements.

A survey on modeling strategies for high-speed differential Via between two parallel plates

This paper presents a survey on physics-based modeling strategies for differential via in high-speed multilayer printed circuits (PCBs). Driven by the goals of accurate and efficient design, researchers have explored several approaches for differential via modeling, include π-type RLC circuit, differential transmission line with via-plate capacitance/effective dielectric constant and parallel plate impedance model. This survey provides overviews of these modeling strategies and comparisons by correlating mixed-mode S-parameter from HFSS. In particular, this paper then aims on building a generic parameterized and SPICE-compatible circuit model for designing differential via in a frequency range up to 40GHz.