Yuebin Huang

An efficient multi-rate LDPC-CC decoder with layered decoding algorithm

An efficient multi-rate Low-Density Parity-Check Convolutional Code decoder will be present in this paper. We will introduce layered decoding algorithm into LDPC-CC decoding. Simulation results shows that our method can achieve better performance than the original brief propagation algorithm with less processors. Besides a new ASIC architecture which adopt proposed algorithm and can support all code rate (1/2, 2/3, 3/4, 4/5) of the LDPC-CC code in IEEE 1901 is proposed. Based on SMIC 130 nm CMOS process, our decoder attaints a maximum throughput of 333.3 Mb/s at 200 MHz. The core area is 3.55 mm2 with 10 processors. The average power consumption is 262 mW at code rate 4/5 and 200 MHz. The VLSI result shows that our decoder is both memory efficient and area efficient.

A high-throughput LDPC decoder for optical communication

As Optical Communication is on the way, conventional LDPC decoders do not work well with the requirement for high throughput over 100 Gb/s. Many new LDPC decoder structures aiming at high throughput have been proposed, such as stochastic decoders, bit serial decoders, digit serial decoders and so forth. In this paper, a Min-Sum fully parallel structure using clock multiplexing is proposed, as an attempt to relieve the wiring problem. This decoder makes full use of clock edges comparing to conventional decoders. With SIMC 0.13um technology, our decoder achieves a throughput of 54.2 Gb/s at 200MHz for the WiMAX standard of 5/6 code rate. Our conjecture is that with lower feature size and higher clock frequency, 100 Gb/s could be achieved.

A robust frame synchronization scheme for Broadband Power-line Communication

In this paper, several frame synchronization schemes is examined under the scenario of Broadband Power-line Communication (BPL) with their merits and demerits illustrated. A method, mainly based on algorithm proposed by Minn with modification, is proposed and simulated under channels proposed by Open PLC European Research Alliance (OPERA). Threshold is set according to simulations for frame synchronization as well as Physical Protocol Data Unit (PPDU) identification. The proposed estimator has a RMS (Root Mean Square) of start point estimation three orders lower at least in comparison with legacy Schmidl and Cox estimator. Optimization schemes are also proposed to increase the hardware efficiency for the estimator. As much as 75% multiplications could be saved with only a slight degradation in estimation accuracy for the proposed estimator.

A low-cost architecture for multi-mode Reed-Solomon decoder

This paper presents a multi-mode Reed-Solomon (RS) decoder with folding architecture which has low cost and low power consumption. The solution can be applied into any application that requires multi-mode RS codes. Implemented by SMIC 0.13 μm 1.2 V CMOS technology, the decoder runs at 440MHz clock rate and has a gate count of 65K and die size of 1.18×1.18 mm2. The power consumption is 0.25mW per error byte benefiting from the proper mode control, which is quite economical for a multi-mode RS decoder. The maximum error correction capability of the decoder is 32 bytes.

A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOS

A highly-parallel LDPC decoder architecture for 10Gbase-T applications is designed in this paper. Firstly, we reduce the routing complexity and corresponding power consumption by the proposed decoder architecture based on single routing networks. Secondly, the proposed architecture is designed with pipelined layered scheduling and multi-block parallel decoding, which improves operation speed and removes pipeline stalls in conventional highly-parallel layered scheduling. Thirdly, we trade off between hardware cost and throughput by a digit-serial data-path. Fourthly, an efficient early-termination circuit suitable for layered decoding is designed. The decoder is implemented in 130nm 1P8M CMOS process. The core area is 18.4mm2 with 14% reduction, and the decoding throughput is 9.48Gbps operating at 278MHz and 5 iterations. The tested power consumption is 774mW at 1.2V and 80MHz.

A common flexible architecture for Turbo/LDPC codes

Turbo codes and LDPC codes are two of the most powerful error correction codes that can approach Shannon limit in many communication systems. But there are little architecture presented to support both LDPC and Turbo codes, especially by the means of ASIC. This paper have implemented a common architecture that can decode LDPC and Turbo codes, and it is capable of supporting the WiMAX, WiFi, 3GPP-LTE standard on the same hardware. In this paper, we will carefully describe how to share memory and logic devices in different operation mode. The chip is design in a 130nm CMOS technology, and the maximum clock frequency can reach up to 160MHz. The maximum throughput is about 104Mbps@5.5 iteration for Turbo codes and 136Mbps@10iteration for LDPC codes. Comparing to other existing structure, the design speed, area have significant advantage.

A 691 Mbps 1.392mm 2 configurable radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems in 65nm CMOS

This paper presents a unified parallel radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems. A radix-16 decoding for both binary and duo-binary turbo codes is proposed to reduce complexity as well as critical path delay. In addition, the two distinct interleavers in the standards are implemented with low-complexity address generator and barrel shift networks. Furthermore, quad-bank memory partition facilitates parallel radix-16 decoding without address conflict. Fabricated in TSMC 65nm CMOS process, the ASIC attains 691Mbps throughput running at 512MHz and 5.5 iterations. For the 326.4Mbps LTE peak data rate, it consumes only 193mW at 0.9V supply voltage with unprecedented energy efficiency of 0.108nJ/bit/iteration.

Flexible and efficient FEC decoders supporting multiple transmission standards

An important trend of the modern mobile device is that a single user terminal that will be capable of receiving signals of multiple different transmission standards. Most of these transmission standards employ a forward error correction decoding, including Reed-Solomon, Viterbi, Turbo and low-density parity check and so on. In this overview paper we review several programmable and area-efficient decoder architectures within one hardware platform. We show, in the case of guaranteed throughput performance, compared with multi-core implementation way, better power consumption performance can be gotten.