Shuji Nishi

P-174L: Late-News Poster: The System-LCD with Monolithic Ambient-Light Sensor System

We describe a newly developed 352×RGB×440 System-LCD that incorporates an ambient light sensor system comprising a lateral photo diode and analog processing circuits integrated directly onto the display substrate in CG-Silicon. By intelligently controlling the LCD backlight level in response to ambient lighting conditions we achieve low power consumption with high reliability at low cost.

Parasitic capacitance modeling for multilevel interconnects

The problem of calculating parasitic capacitance between interconnects is investigated with the main theme focused on deriving approximate expressions for calculating parasitic capacitance between two crossing interconnects. The interconnects are divided into a few basic coupling regions, in such a way that the capacitance in a region can be represented by a simple expression adjusted to the results computed by an electromagnetic field solver based on a two-dimensional capacitance model. An approximate expression of the total capacitance between two crossing interconnects is obtained by summing the capacitances in all regions. In order to evaluate the accuracy of this approximation, the capacitance calculated by the attained expression is compared with the one obtained by a three-dimensional field solver, and it turns out that the error is less than 5%.

An automatic layout method for timing pulse generator of small LCD driver

Driver circuit of the small Liquid Crystal Display (LCD) is formed on the same glass substrate as LCD by means of the so-called SoG (System on Glass) technology. The timing pulse generator of LCD driver, which is to generate trigger signals for driving each pixel, is usually laid out restrictedly in an area remaining after the layout of other subcircuits in LCD driver. Thus, if the design automation dedicated for layout of this timing pulse generator is devised, then the quality as well as the cost of a total design of LCD driver can be greatly improved. This paper describes an automatic layout method for the timing pulse generator by adopting existing placement and routing tools. The application of this automatic layout method to the timing pulse generator can yield the high-performance layout equivalent to manual design in a practical runtime.