Shun Kawabe

Clock event suppression algorithm of VELVET and its application to S-820 development

An advanced clock event suppression algorithm for high-speed logic simulation is described. A signal value, Cn, and a current clock (CC), which indicates the current status of clock signals, has been introduced to realize this algorithm. This algorithm suppresses about 60% of the total events, and eliminates 40% of CPU time. No overhead is needed to incorporate this algorithm using hardware support of VELVET (vectorized processing system for logic verification). Hitachis latest supercomputer S-820 has been developed using VELVET. The development period has been shortened to 3/4 that of the S-810.<<ETX>>

An Overview of the HITACHI S-3800 Series Supercomputer

Hitachi Ltd. has developed a world-class supercomputer group, the HITACHI S-3000 Series, to meet accelerating demands for higher performance, larger system capacity and greater fitness with established development environments in engineering/scientific community. It comes in two subgroups, the water-cooled S-3800 and the air-cooled S-3600, each consisting of several models. Built on leading-edge hardware technologies, and comprising multiple scalar as well as vector engines, the top-of-the-line S-3800/480 delivers a maximum arithmetic throughput of 32 GFLOPS, an order of magnitude higher than that of the predecessor group S-820. The Series operates under an OSF/1 version of the UNIX® operating system, which provides the users with easy access to a variety of established application packages, as well as Hitachi’s proprietary VOS3/AS. To allow communications with other computing resources and high-power workstations via a high speed network, the Series supports the HIPPI interface. For quick visualization of simulation results, the real-time animation feature developed first for the S-820 is also available.

High-speed processing schemes for summation type and iteration type vector instructions on Hitachi supercomputer S-820 system

The HITACHI supercomputer S-820 system has been developed as Hitachis top end supercomputer. It is also rated as one of the most powerful supercomputers in the world. Among the vector instructions which supercomputers support, summation type vector instructions and iteration type vector instructions are not suitable for parallel processing, since elements to be processed are not independent in these instructions. The S-820 employs high-speed processing schemes for summation type vector instructions and iteration type vector instructions; the performance of summation type instructions is enhanced by high-speed post-processing scheme and the performance of iteration type instructions is enhanced by high-speed parallelizing scheme for iteration arithmetic. Thanks to these schemes, the execution speeds for Kernel 3 and Kernel 4 of the Lawrence Livermore Laboratorys 24 Kernels become 838.7 MFLOPS and 258.5 MFLOPS respectively, and those for Kernel 5, Kernel 6 and Kernel 11 of the Lawrence Livermore Laboratorys 14 Kernels become 114.6 MFLOPS, 111.8 MFLOPS and 98.4 MFLOPS, respectively.

A relational database system architecture based on a vector processing method

A new relational database system architecture based on a vector processing method is presented. The similarity between table and vector structures was studied. This similarity implies that vector processors have high potential for the improvement of Relational Data Base Management System (RDBMS) performance. In commercial RDBMSs, however, data records are internally organized in complex pointer structures, to which vector processing is not directly applicable. We propose a new vectorization method by which data in the pointer structures are dynamically rearranged into vector form, and collectively processed using a pipelined vector processor. A new pipelined vector processor called an Integrated Database Processor (IDP) which is particularly suitable for our vectorization strategy was developed. IDP is designed as an optional hardware for a general purpose computer. The vectorization method and IDP are applied to Hitachis new, recently-announced, commercial RDBMS (called RDB1/IDP). In this paper, the vectorization method and the architecture of IDP are described. The performance improvement is also described and analyzed.

High-speed storage control schemes of HITACHI supercomputer S-820 system

The HITACHI supercomputer S-820 has been developed as Hitachis top end supercomputer. It is also rated as one of the most powerful supercomputers in the world. To match high performance of arithmetic units, the S-820 employed advanced storage control schemes. Of these schemes, this paper introduces the parallel structure of the storage control, section number assigning, bank group number modifying and vector indirect store instruction. By parallel structure of the storage control and section number assigning, peak memory throughput of 16 Gbytes/sec is achieved. By bank group number modifying, critical memory access conflicts are avoided and excellent memory throughput is achieved especially for vectors with short strides. By using vector indirect store instruction, the performance of store-type list vector operation without duplicated list vector elements is 2.3-fold improved over that obtained by using conventional store-type list vector instructions.

A relational database system architecture based on a vector-processing method

A new relational database system architecture based on a vector processing method is presented. The similarity between table and vector structures was studied. This similarity implies that vector processors have high potential for the improvement of Relational Data Base Management System (RDBMS) performance. In commercial RDBMSs, however, data records are internally organized in complex pointer structures, to which vector processing is not directly applicable. We propose a new vectorization method by which data in the pointer structures are dynamically rearranged into vector form, and collectively processed using a pipelined vector processor. A new pipelined vector processor called an Integrated Database Processor (IDP) which is particularly suitable for our vectorization strategy was developed. IDP is designed as an optional hardware for a general purpose computer. The vectorization method and IDP are applied to Hitachis new, recently-announced, commercial RDBMS (called RDB1/IDP). In this paper, the vectorization method and the architecture of IDP are described. The performance improvement is also described and analyzed.

Hitachi S-820 supercomputer system

The HITACHI S-820 made a debut as one of the most powerful supercomputers in the world in 1987. It consists of a Scalar Processor and a Vector Processor. As the Scalar Processor has the same architecture as a general-purpose mainframe, the whole complex fits well in conventional operating environments. Central to the high computation speed is the Vector Processor with its multiple-pipeline structure and large vector register memory. The use of the semiconductor Extended Storage dramatically reduces I/O time, contributing to faster job turn around and balanced system performance. A high degree of parallelism is incorporated inside the Vector Processor as well as between the Vector and the Scalar Processors. The hardware technology employed in the system, which is the key to high performance and supreme reliability, includes the field-proven state-of-the-art high-speed logic LSIs originally developed for Hitachi’s large-scale mainframes, a 256 Kbits BiCMOS with an access time of 20 nsec, and a vector register LSI which combines logic and RAMs on a monolithic chip. A variety of software products has also been developed to fully exploit the hardware capabilities.

An Overview of the HITACHI S-820 Supercomputer System

The HITACHI S-820 has made a debut as one of the most powerful supercomputers in the world, with a peak arithmetic performance of 3 GFLOPS. Like its predecessor S-810, the first Japanese-made supercomputer, it consists of a scalar processor and a vector processor. As the scalar processor has the same architecture as a general-purpose mainframe, the whole complex fits well in conventional operating environments. Central to the high computation speed is the vector processor with its multiple-pipeline structure and large vector register memory. The use of the semiconductor Extended Storage dramatically reduces I/O time, contributing to faster job turnaround and balanced system performance. A high degree of parallelism is incorporated inside the vector processor as well as between the vector and the scalar processors. The hardware technology employed in the system, which is the key to high performance and supreme reliability, includes the field-proven state-of-the-art high-speed logic LSIs originally developed for Hitachi’s top-of-the-line mainframes, a 256K bit CMOS RAM with an access time of 45 nsec, and a vector register LSI which combines logic and RAMs on a monolithic chip. A variety of software products have also been developed to fully exploit the hardware capabilities. They include a vectorizing compiler FORT77/HAP with enhanced vectorization capability, an easy-to-code differential equation solver DEQSOL E2, and a mathematical subroutine library MATRIX/HAP. In a benchmark with Lawrence Livermore Laboratory’s 14 Kernels, the S-820 scores 355 (417 with a biCMOS version of the Main Storage) MFLOPS (algebraic average), among the highest in the industry.