Shuo Sheng

Efficient spectral techniques for sequential ATPG

We present a new test generation procedure for sequential circuits using spectral techniques. Iterative processes of filtering via compaction and spectral analysis of the filtered test set are performed for each primary input, extracting inherent spectral information embedded within the test sequence. This information, when viewed in the frequency domain, reveals the characteristics of the input spectrum. The filtered and analyzed set of vectors is then used to predict and generate future vectors. We also developed a fault-dropping technique to speed up the process. We show that very high fault coverages and small vector sets are consistently obtained in short execution times for sequential benchmark circuits.

A novel SAT all-solutions solver for efficient preimage computation

In this paper, we present a novel all-solutions preimage SAT solver, SOLALL, with the following features: (1) a new success-driven learning algorithm employing smaller cut sets; (2) a marked CNF database non-trivially combining success/conflict-driven learning; (3) quantified-jump-back dynamically quantifying primary input variables from the preimage; (4) improved free BDD built on the fly, saving memory and avoiding inclusion of PI variables; finally, (5) a practical method of storing all solutions into a canonical OBDD format. Experimental results demonstrated the efficiency of the proposed approach for very large sequential circuits.

Efficient Preimage Computation Using A Novel Success-Driven ATPG

Preimage computation is a key step in formal verification. Pure OBDD-based symbolic method is vulnerable to the space-explosion problem. On the other hand, conventional ATPG/SAT-based method can handle large designs but can suffer from time explosion. Unlike methods that combine ATPG/SAT and OBDD, we present a novel success-driven learning algorithm which significantly accelerates an ATPG engine for enumerating all solutions (preimages). The algorithm effectively prunes redundant search space due to overlapped solutions and constructs a free BDD on the fly so that it becomes the representation of the preimage set at the end. Experimental results have demonstrated the effectiveness of the approach, in which we are able to compute preimages for large sequential circuits, where OBDD-based methods fail.

Novel spectral methods for built-in self-test in a system-on-a-chip environment

This new method of built-in self-test (BIST) for sequential cores on a system-on-a-chip (SOC) generates test patterns using a real-time program that runs on an embedded processor. Alternatively, the same program can be run on an external low-cost tester. This program generates patterns using circuit-specific spectral information in the form of one or more Hadamard coefficients. The coefficients are extracted from high fault-coverage compacted pattern sets. When an embedded processor is available on SOC, the overhead is negligible. Also, sequential cores are tested in the functional mode, avoiding activation of nonfunctional timing paths. We present experimental results to show that for hard to test circuits, with any given test time, spectral patterns provide significantly higher fault coverage than weighted-random patterns.

Efficient sequential test generation based on logic simulation

In this article, we present an efficient logic-simulation-based test generator that executes significantly more quickly than its fault-simulation-based counterparts. This test generators fault coverage compares favorably with that of the latest techniques for large sequential circuits. It uses a genetic algorithm to achieve both high fault coverage and short test generation times.

Compaction-based test generation using state and fault information

Presents a new test generation procedure for sequential circuits using newly-traversed state information and newly-detected fault information obtained between successive iterations of vector compaction. Two types of technique are considered. One is based on which new states a sequential circuit is driven into, and the other is based on the new faults that are detected in the circuit between consecutive iterations of vector compaction. These data modify an otherwise random selection of vectors to bias vector sequences that cause the circuit to reach new states and cause previously undetected faults to be detected. The biased vectors, when used to extend the compacted test set, provide an intelligent selection of vectors. The extended test set is then compacted. Repeated applications of state and fault analysis, vector generation and compaction produce significantly high fault coverage using relatively small computing resources. We obtained improvements in terms of higher fault coverage, fewer vectors for the same coverage, or smaller numbers of iterations and time required, consistently for several benchmark circuits.

Success-driven learning in ATPG for preimage computation

Unbounded model checking fundamentally requires either image or preimage calculations. We introduce a hybrid method for making preimage calculations using ATPG and binary decision diagrams (BDDs). Experimental results show that the proposed method achieves a speedup of two to three orders of magnitude over pure ATPG methods.

State and Fault Information for Compaction-Based Test Generation

We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vector compaction. Two types of techniques are considered. One is based on the new states a sequential circuit is driven into, and the other is based on the new faults that are detected between consecutive iterations of vector compaction. These data modify an otherwise random selection of vectors, to bias vector sequences that cause the circuit to reach new states, and cause previously undetected faults to be detected. The biased vectors, when used to extend the compacted test set, provide a more intelligent selection of vectors. The extended test set is then compacted. Repeated applications of state and fault analysis, vector generation and compaction produce significantly high fault coverage using relatively small computing resources. We obtained improvements in terms of higher fault coverage, fewer vectors for the same coverage, or smaller number of iterations and time required, consistently for several benchmark circuits.

Verification of large scale nano systems with unreliable nano devices

Any nano-system that designers build must guarantee functional correctness. The sheer scale factor and the added layers of uncertainty in nano-systems demand revolutionary breakthroughs in system design tools and algorithms. Formal verification of nano systems, then, must be able to deal with large state spaces, together with the presence of unknowns and uncertainties. The methods described in this chapter present a suite of algorithms that can offer potential in reducing the problem complexity in verification of nano-systems.