Shuou Nomura
Toshiba
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Featured researches published by Shuou Nomura.
international solid-state circuits conference | 2005
Toshihide Fujiyoshi; Shinichiro Shiratake; Shuou Nomura; Tsuyoshi Nishikawa; Yoshiyuki Kitasho; Hideho Arakida; Yuji Okuda; Yoshiro Tsuboi; Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Fumitoshi Hatori; Takayoshi Shimazawa; Kunihiko Yahagi; Hideki Takeda; Masami Murakata; Fumihiro Minami; Naoyuki Kawabe; Takeshi Kitahara; Katsuhiro Seta; Masafumi Takahashi; Yukihito Oowaki; Tohru Furuyama
A single-chip H.264 and MPEG-4 audio-visual LSI for mobile applications including terrestrial digital broadcasting system (ISDB-T / DVB-H) with a module-wise, dynamic voltage/frequency scaling architecture is presented for the first time. This LSI can keep operating even during the voltage/frequency transition, so there is no performance overhead. It is realized through a dynamic deskewing system and an on-chip voltage regulator with slew rate control. By the combination with traditional low power techniques such as embedded DRAM and clock gating, it consumes only 63 mW in decoding QVGA H.264 video at 15 frames/sec and MPEG-4 AAC LC audio simultaneously.
international solid-state circuits conference | 2008
Shuou Nomura; Fumihiko Tachibana; Tetsuya Fujita; Chen Kong Teh; Hiroyuki Usui; Fumiyuki Yamane; Yukimasa Miyamoto; Chaiyasit Kumtornkittikul; Hiroyuki Hara; Takahiro Yamashita; Jun Tanabe; Masato Uchiyama; Yoshiro Tsuboi; Takashi Miyamori; Takeshi Kitahara; Hironori Sato; Yuya Homma; Shuuji Matsumoto; Keiko Seki; Yoshinori Watanabe; Mototsugu Hamada; Masafumi Takahashi
A AAC-decoding, H.264 decoding, media processor with embedded forward-body-biasing and power-gating circuit in CMOS technology is proposed. Since all the components necessary for the scheme are simple MOS circuits requiring no extra supply voltages, they can be placed and routed by a commercial CAD tool. A data-mapping flip-flop was proposed as a high performance and low-power flip-flop. It is concluded that the power dissipation in H.264 720p 60fps decoding of 620mW at the process fast corner is the lowest among the processor-based solutions.
custom integrated circuits conference | 2008
Fumihiko Tachibana; Hironori Sato; Takahiro Yamashita; Hiroyuki Hara; Takeshi Kitahara; Shuou Nomura; Fumiyuki Yamane; Yoshiro Tsuboi; Keiko Seki; Shuuji Matsumoto; Yoshinori Watanabe; Mototsugu Hamada
A cell-based forward body-biasing technique to suppress the global process variation and its design flow are proposed. Latch-up free operation is guaranteed by embedded current source cells and limiter cells even when supply voltage is 1.2 V with small area overhead. By applying this technique to a media processor, the worst-case delay is reduced by 20% without sacrificing the maximum leakage spec.
international conference on ic design and technology | 2009
Shuou Nomura; Fumihiko Tachibana; Tetsuya Fujita; Chen Kong Teh; Hiroyuki Usui; Fumiyuki Yamane; Yukimasa Miyamoto; Takahiro Yamashita; Hiroyuki Hara; Mototsugu Hamada; Yoshiro Tsuboi
A multi-core co-processor for mobile application processors is introduced. It provides low-power, high-throughput, fully software-based acceleration of multimedia processing. The test chip fabricated in a 65nm CMOS technology consumes 620mW in H.264 720p 60fps decoding and 9.7mW in MPEG-4 AAC decoding. In the maximum workload of H.264 decoding, a symmetrical parallelization achieves 7.5× performance enhancement by 8 cores. The shared L2 cache reduces the required rate of main memory access to 310MB/s. In the minimum workload of AAC decoding, three low-power circuit techniques reduce 98% of leakage. On-chip regulators, which also work as power-gating switches, lower the supply voltage of processing cores. Embedded forward body-biasing circuit reduces Vt variations. A low-power and fast data-mapping F/F relaxes the timing constraint, which enables a reduction in the number of low-Vt transistors.
custom integrated circuits conference | 1988
K. Terashima; Y. Fujita; Shuou Nomura; H. Kisigami
An analog front end LSI for 9600/4800-b/s modems has been developed. To reduce total error rate, group delay time equalizers (GDT-EQLs) for bandlimiting filters are integrated on the chip. Noise level is suppressed to -77 dBm without the GDT-EQL. Relative GDT characteristics of Tx and Rx filters are less than 80 mu s in the frequency range from 800 Hz to 3.0 kHz.<<ETX>>
Archive | 2006
Shuou Nomura
Archive | 2006
Shuou Nomura
Archive | 2017
Hajime Matsui; Shuou Nomura; Akira Moriya
Archive | 2017
Kazuki Inoue; Kohei Oikawa; Yukimasa Miyamoto; Kosuke Hatsuda; Shuou Nomura; Kojiro Suzuki
Archive | 2016
Hajime Matsui; Youhei Fukazawa; Shuou Nomura; Shunichi Ishiwata; Takaya Ogawa; Atsushi Mochizuki; Kazuyo Kanou; Akira Moriya; Yoshiro Tsuboi