Mototsugu Hamada

A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

This MPEG4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power dissipation of a conventional CMOS design. Measured power dissipation is summarized. 70% power reduction is achieved by low-power techniques at circuit and architectural levels. A 16b RISC processor provides software programmability. Binary shape decoding uses 20% of the computation power of the RISC processor at 30MHz clock, with negligible increase in chip power dissipation. Three-step hierarchical motion estimation reduces power dissipation.

A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

A novel design technique which combines a variable supply-voltage scheme and a clustered voltage scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay and area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit performance compared to a conventional CMOS design.

Utilizing surplus timing for power reduction

Multiple Vdds, multiple Vths, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdds, Vths, and Ws are derived, as well as knowledge for future design.

A 19.7 MHz, Fifth-Order Active- RC Chebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme

A fifth-order LPF with a quality factor (Q) tuning circuit has been implemented for draft IEEE802.11n in a 0.13 CMOS technology. The proposed Q tuning technique realizes a low-power 19.7 MHz, active-RC Chebyshev LPF. The filter has dB gain, 30 nV/Hz1/2 input-referred noise, 113 dBmuV input , P 1dB,draws 7.5 mA current from 1.5 V supply, and occupies an area of 0.2 mm2.

A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM

A 240 mW single-chip MPEG-4 video-phone LSI with a 16 Mb embedded DRAM is fabricated in a 0.25 /spl mu/m CMOS, triple-well, quad-metal technology. The chip integrates a 16 Mb DRAM and three dedicated 16 b RISC processors with dedicated hardware accelerators that serve as an MPEG-4 video codec, a speech codec, and a multiplexer. It also integrates camera, display, and audio interfaces required for a video-phone system. It consumes 240 mW at 60 MHz operation, which is only 22% of the power dissipation of a conventional design. A variable threshold voltage CMOS (VTCMOS) technology is employed to reduce standby leakage current to 26 /spl mu/A, which is only 17% of the conventional CMOS design.

Low-power CMOS digital design with dual embedded adaptive power supplies

A low-power CMOS design methodology with dual embedded adaptive power supplies is presented. A variable supply-voltage scheme for dual power supplies, namely, the dual-VS scheme, is presented. It is found that the lower supply voltage should be set at 0.7 of the higher supply voltage to minimize chip power dissipation. This knowledge aids designers in the decision of the optimal supply voltages within a restricted design time. An MEPG-4 video codec chip is designed at 2.5 and 1.75 V for internal circuits that are generated from an external power supply of 3.3 V by the dual-VS circuits. Power dissipation is reduced by 57% without degrading circuit performance compared to a conventional CMOS design.

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems

This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We present two CDMFFs, having differential and single-ended structures, respectively, and compare them to the state-of-the-art flip-flops. The results indicate that both CDMFFs have the best power-delay product in their groups, respectively. In the aspect of power dissipation, the single-ended and differential CDMFFs consume the least power at data activity less than 50%, and are 31% and 26% less power than the conditional capture flip-flops at 25% data activity, respectively. In the aspect of performance, CDMFFs achieve small data-to-output delays, comparable to those of the transmission-gate pulsed latch and the modified-sense-amplifier flip-flop. In the aspect of timing reliability, CDMFFs have the best internal race immunity among pulse-triggered flip-flops. A post-layout case study is demonstrated with comparison to a transmission-gate flip-flop. The results indicate the single-ended CDMFF has 34% less in data-to-output delay and 28% less in power at 25% data activity, in spite of the 34% increase in size

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

This paper describes a fully automated low-power design methodology in which three different voltage-scaling techniques are combined together. Supply voltage is scaled globally, selectively, and adaptively while keeping the performance. This methodology enabled us to design an MPEG4 codec core with 58% less power than the original in three week turn-around-time.

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling

A single-chip H.264 and MPEG-4 audio-visual LSI for mobile applications including terrestrial digital broadcasting system (ISDB-T / DVB-H) with a module-wise, dynamic voltage/frequency scaling architecture is presented for the first time. This LSI can keep operating even during the voltage/frequency transition, so there is no performance overhead. It is realized through a dynamic deskewing system and an on-chip voltage regulator with slew rate control. By the combination with traditional low power techniques such as embedded DRAM and clock gating, it consumes only 63 mW in decoding QVGA H.264 video at 15 frames/sec and MPEG-4 AAC LC audio simultaneously.

A single-chip CMOS Bluetooth transceiver with 1.5MHz IF and direct modulation transmitter

A single-chip Bluetooth transceiver in 0.18/spl mu/m CMOS integrates a direct VCO modulation transmitter and 1.5MHz-IF receiver to reduce power consumption and cost. The receiver achieves a sensitivity of -77dBm and transmitting power of +4dBm.