Fumiyuki Yamane

Variable supply-voltage scheme for low-power high-speed CMOS digital design

This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-/spl mu/m CMOS technology which optimally controls the internal supple voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.

A 300 MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS

A 300 MIPS/W RISC core processor with variable supply-voltage (VS) scheme in variable threshold-voltage CMOS (VTCMOS) is presented. Performance in MIPS/W can be improved by a factor of more than two with no modification in the RISC core except for substrate contacts for the VTCMOS. From a 3.3 V external power supply the VS scheme automatically generates minimum internal supply voltages which meet the demand on its operation frequency.

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology

A AAC-decoding, H.264 decoding, media processor with embedded forward-body-biasing and power-gating circuit in CMOS technology is proposed. Since all the components necessary for the scheme are simple MOS circuits requiring no extra supply voltages, they can be placed and routed by a commercial CAD tool. A data-mapping flip-flop was proposed as a high performance and low-power flip-flop. It is concluded that the power dissipation in H.264 720p 60fps decoding of 620mW at the process fast corner is the lowest among the processor-based solutions.

A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design

A cell-based forward body-biasing technique to suppress the global process variation and its design flow are proposed. Latch-up free operation is guaranteed by embedded current source cells and limiter cells even when supply voltage is 1.2 V with small area overhead. By applying this technique to a media processor, the worst-case delay is reduced by 20% without sacrificing the maximum leakage spec.

A low-power multi-core media co-processor for mobile application processors

A multi-core co-processor for mobile application processors is introduced. It provides low-power, high-throughput, fully software-based acceleration of multimedia processing. The test chip fabricated in a 65nm CMOS technology consumes 620mW in H.264 720p 60fps decoding and 9.7mW in MPEG-4 AAC decoding. In the maximum workload of H.264 decoding, a symmetrical parallelization achieves 7.5× performance enhancement by 8 cores. The shared L2 cache reduces the required rate of main memory access to 310MB/s. In the minimum workload of AAC decoding, three low-power circuit techniques reduce 98% of leakage. On-chip regulators, which also work as power-gating switches, lower the supply voltage of processing cores. Embedded forward body-biasing circuit reduces Vt variations. A low-power and fast data-mapping F/F relaxes the timing constraint, which enables a reduction in the number of low-Vt transistors.