Shuso Fujii

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ¿m2. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.

Fault-tolerant designs for 256 Mb DRAM

This paper describes fault-tolerant designs, which have been used to boost the yield of a 286 mm/sup 2/ 256 Mb DRAM with x32 both-ends DQ. The 256 Mb DRAM consists of sixteen 16 Mb units, each containing one 128 Kb row redundancy block. This row redundancy block architecture allows flexible row redundancy replacement, where random faults, clustered faults, and grouped faults can be efficiently repaired. Flexible column redundancy replacement with interchangeable master DQs (MDQ) is used to allow a 256 b data compression without causing a data conflict, while improving the column access speed by 2 ns. A depletion NMOS bitline-precharge-current-limiter suppresses the current flow which occurs as a result of a wordline-bitline short-circuit to only 15 /spl mu/A per cross fail, avoiding a standby current fail. Consequently, the hardware results show a significant yield enhancement of 16 times relative to the intra-block/segment replacement. Detailed simulation results show that this 256 Mb DRAM allows 275 random faults to be repaired with 5.5% silicon area overhead for 80% chip yield.

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode

A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm2 die with an effective cell-size of 0.7191mum2 while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst

Flexible test mode approach for 256-Mb DRAM

This paper describes a flexible test mode approach developed for a 256-Mb dynamic random access memory (DRAM). Test mode flexibility is achieved by breaking down complicated test mode control into more than one primitive test mode. The primitive test modes can be selected together through a WE CAS Before RAS (WCBR) cycle with a series of addresses for mode select. Although each primitive test mode may not complete a meaningful task alone, their combination performs many complex and powerful test modes. In this design, 64 primitive test modes are available. These can be combined to realize more than 19000 useful test modes. A new signal margin test mode is introduced which allows an accurate signal margin test even for small capacitance cells, which are difficult to identify in existing plate-bump method. A flexible multiwordline select test mode effectively performs a toggled wordline disturb test, a long t/sub RAS/ wordline disturb test, and a transfer gate stress voltage test, without causing any unnatural array disturbance. Finally, test modes, which can directly control the timing of sense amplifiers and column select lines, are discussed.

Melt-segregate-quench programming of electrical fuse

We propose a novel electrical fuse (e-fuse) programming procedure with a melt-segregate-quench mechanism by applying a short and large current pulse. This mechanism enables a dramatic shortening of programming time. Experimental results and thermal conduction analysis are introduced for 90 nm technology.

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode

A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-“0”-write-before-data-write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm2 with average cell size of 0.7191 μm2.

A 128Mb Floating Body RAM(FBRAM) on SOI with Multi-Averaging Scheme of Dummy Cell

A 128Mbit FBRAM using the floating body cell (FBC) the size of 0.17mum² (6.24F² with F=0.165mum) was successfully fabricated and a high bit yield (~99.999%) was obtained

Flexible test mode design for DRAM characterization

Testing is a crucial process in the development and production of VLSI memory chips. On-chip test modes not only reduce manufacturing test time, but also allow effective debugging of the technology during the development phase. This paper describes the flexible test modes deployed in our fully functional 256 Mb DRAM chip.

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance

This paper demonstrates the hard disk drive (HDD) performance improvement by nonvolatile FeRAM cache. First, an array architecture and data path design of 128 Mb chain FeRAM to meet HDD specifications, and a total power supply system for HDD application are presented. A 1.6 GB/s read/write bandwidth with page length of 512 Byte HDD sector size, and the data protection against sudden power failure have been realized. Second, the concept of nonvolatile FeRAM cache to utilize cache memory to the maximum by ignoring flush cache commands issued from Windows OS is presented. Third, the simulated and measured HDD performance improvements are demonstrated. The read/write bandwidth improvements by 1.12 times, 3.3 times and 1.9 times have been verified by two benchmark tests of PC Mark 05 and the copy of FD Bench v1.01, and by simulation using the PC user data for five days, respectively. These results are at the same levels of, or more effective than, the results of HDD disk rotational speed-up from 5400 rpm to 7200 rpm using a DRAM cache. The write energy is also reduced by 25% in PC Mark05 test.

A 286 mm/sup 2/ 256 Mb DRAM with /spl times/32 both-ends DQ

This paper describes a 256 Mb DRAM chip architecture which provides up to /spl times/32 wide organization. In order to minimize the die size, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25 /spl mu/m CMOS technology. The chip measures 13.25 mm/spl times/21.55 mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe (RAS) access time of 26 ns was obtained under 2.8 V power supply and 85/spl deg/C. In addition, a 100 MHz/spl times/32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output (EDO) cycle has been successfully demonstrated.