Kosuke Hatsuda

Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ¿m2. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.

FBC's Potential of 6F 2 Single Cell Operation in Multi-Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin

A 6F2 single cell (one-cell-per-bit) operation of the floating body RAM (FBRAM) is successfully demonstrated for the first time with more than 60% yield of 16Mbit area in a wafer. The signal sense margin (SSM) at actual read conditions is found to well back up the functional results. The parasitic resistance in the source and drain formed under the FBCs spacers can be optimized for making the SSM as large as 8muA at plusmn 4.5sigma without sacrificing the retention time.

A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability

A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage

A 333MHz random cycle DRAM using the floating body cell

A Monte Carlo simulation shows that a DRAM using the floating body cell (FEC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and optimization of its current mirror ratio. Since the FEC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FEC is a promising candidate for next generation embedded DRAM cells

A 128Mb Floating Body RAM(FBRAM) on SOI with Multi-Averaging Scheme of Dummy Cell

A 128Mbit FBRAM using the floating body cell (FBC) the size of 0.17mum² (6.24F² with F=0.165mum) was successfully fabricated and a high bit yield (~99.999%) was obtained

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance

This paper demonstrates the hard disk drive (HDD) performance improvement by nonvolatile FeRAM cache. First, an array architecture and data path design of 128 Mb chain FeRAM to meet HDD specifications, and a total power supply system for HDD application are presented. A 1.6 GB/s read/write bandwidth with page length of 512 Byte HDD sector size, and the data protection against sudden power failure have been realized. Second, the concept of nonvolatile FeRAM cache to utilize cache memory to the maximum by ignoring flush cache commands issued from Windows OS is presented. Third, the simulated and measured HDD performance improvements are demonstrated. The read/write bandwidth improvements by 1.12 times, 3.3 times and 1.9 times have been verified by two benchmark tests of PC Mark 05 and the copy of FD Bench v1.01, and by simulation using the PC user data for five days, respectively. These results are at the same levels of, or more effective than, the results of HDD disk rotational speed-up from 5400 rpm to 7200 rpm using a DRAM cache. The write energy is also reduced by 25% in PC Mark05 test.

A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

A 128Mb SOI DRAM with FBC (floating body cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i) In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii) Cu wiring has been used for bit line (BL) and source line (SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS technology

A 128Mb ChainFeRAM TM and system designs for HDD application and enhanced HDD performance

This paper demonstrates the hard disk drive (HDD) performance improvement by nonvolatile FeRAM cache. First, the 128Mb ChainFeRAMTM design and power supply system design to meet HDD application are presented. Second, the concept of nonvolatile FeRAM cache and the simulated and measured HDD performance improvement are presented. The read/write bandwidth improvements to 1.12 times, 3.3 times and 1.9 times have been obtained by bench mark tests of PC Mark 05 and FD Bench v1.01, and by PC user data for 5 days, respectively. These results have been the same level of or more effective than the results of HDD rotational speed-up from 5400rpm to 7200rpm using DRAM cache. The write energy is reduced by 25% in PC Mark05 test.

A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology Node for Embedded Applications

Floating body cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128Mb SOI DRAM with FBC has been designed and successfully developed. The memory cell design and the experimental results, such as the signal and the retention characteristics, are reviewed. The results of the fabricated SOI DRAM and the prospect as embedded memory are also discussed