Shuu'ichirou Yamamoto

Nonvolatile Static Random Access Memory Using Magnetic Tunnel Junctions with Current-Induced Magnetization Switching Architecture

We propose and computationally analyze a nonvolatile static random access memory (NV-SRAM) cell using magnetic tunnel junctions (MTJs) with magnetic-field-free current-induced magnetization switching (CIMS) architecture. A pair of MTJs connected to the storage nodes of a standard SRAM cell with CIMS architecture enables fully electrical store and restore operations for nonvolatile logic information. A wide range of tunneling magnetoresistance (TMR) ratios and Vhalf (the bias voltage when the TMR ratio is reduced to half its original value) values are acceptable for the operation of the proposed NV-SRAM cell. Successful operation can be easily achieved when moderate TMR and Vhalf values such as 100% and 100 mV, respectively, are used. The proposed NV-SRAM is expected to be a key component of next-generation power-gating logic systems with extremely low static-power dissipation.

Nonvolatile static random access memory based on spin-transistor architecture

The authors proposed and computationally analyzed nonvolatile static random access memory (NV-SRAM) architecture using a new type of spin transistor comprised of a metal-oxide-semiconductor field-effect transistor (MOSFET) and magnetic tunnel junction (MTJ) that is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit approach to reproduce the functions of spin transistors, based on recently progressed magnetoresistive random access memory technology. The proposed NV-SRAM cell can be simply configured by connecting two PS-MOSFETs to the storage nodes of a standard SRAM cell.The authors proposed and computationally analyzed nonvolatile static random access memory (NV-SRAM) architecture using a new type of spin transistor comprised of a metal-oxide-semiconductor field-effect transistor (MOSFET) and magnetic tunnel junction (MTJ) that is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit approach to reproduce the functions of spin transistors, based on recently progressed magnetoresistive random access memory technology. The proposed NV-SRAM cell can be simply configured by connecting two PS-MOSFETs to the storage nodes of a standard SRAM cell.

Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices

The paper presents functional MOSFET (F-MOSFET) architecture using nonpolar-type resistive switching devices (RSDs) for nonvolatile SRAM (NV-SRAM) application. The architecture can be achieved by connecting a RSD to the source terminal of an ordinary MOSFET. The current drive capability of the F-MOSFET can be modified by the resistance state of the connected RSD, which is a very useful function for recently emerging nonvolatile logic and reconfigurable logic applications. NV-SRAM can be easily configured with a standard SRAM cell and F-MOSFETs. Using our developed SPICE macromodel for nonpolar-type RSDs, the circuit operation of the proposed NV-SRAM cell was computationally simulated.

Nonvolatile Delay Flip-Flop Based on Spin-Transistor Architecture and Its Power-Gating Applications

We propose and computationally analyze a new type of nonvolatile delay flip-flop (NV-DFF) based on spin-transistor architecture, in which pseudo-spintransistors consisting of an ordinary metal–oxide–semiconductor filed-effect transistor (MOSFET) and a magnetic tunnel junction, referred to as pseudo-spin-MOSFETs are used as a functional nonvolatile storage element. The proposed circuit not only operates as an ordinary DFF, but also is shut down without losing its data. The NV-DFF has only slight increases in circuit delay and layout area within 10% in comparison with an ordinary DFF. Analysis of break-even time (one of the indices for evaluating power-gating efficiency) reveals that the proposed NV-DFF is acceptable for power-gating architecture.

A New Spin-Functional Metal–Oxide–Semiconductor Field-Effect Transistor Based on Magnetic Tunnel Junction Technology: Pseudo-Spin-MOSFET

We fabricated and characterized a new spin-functional metal–oxide–semiconductor field-effect transistor (MOSFET) referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit using an ordinary MOSFET and magnetic tunnel junction (MTJ) for reproducing functions of spin-transistors. Device integration techniques for a bottom gate MOSFET using a silicon-on-insulator (SOI) substrate and for an MTJ with a full-Heusler alloy electrode and MgO tunnel barrier were developed. The fabricated PS-MOSFET exhibited high and low transconductance controlled by the magnetization configurations of the MTJ at room temperature. This is the first observation of spin-transistor operations for spin-functional MOSFETs.

Nonvolatile Power-Gating Field-Programmable Gate Array Using Nonvolatile Static Random Access Memory and Nonvolatile Flip-Flops Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

We proposed and computationally analyzed a nonvolatile power-gating field-programmable gate array (NVPG-FPGA) based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits of the NVPG-FPGA. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power gating (PG). The break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET, which allows highly efficient PG operations with fine granularity, were proposed.

Nonvolatile Static Random Access Memory Using Resistive Switching Devices: Variable-Transconductance Metal–Oxide–Semiconductor Field-Effect-Transistor Approach

In this paper, we present a variable-transconductance (gm) metal–oxide–semiconductor field-effect-transistor (VGm-MOSFET) architecture using a nonpolar resistive switching device (RSD) for nonvolatile bistable circuit applications. The architecture can be achieved by connecting an RSD to the source terminal of an ordinary MOSFET. The current drive capability of the VGm-MOSFET can be modified by resistance states of the connected RSD, which is a very useful function for nonvolatile bistable circuits, such as nonvolatile static random access memory (NV-SRAM) and nonvolatile flip-flop (NV-FF). NV-SRAM can be easily configured by connecting two additional VGm-MOSFETs to the storage nodes of a standard SRAM cell. Using our developed SPICE macromodel for nonpolar RSDs, successful circuit operations of the proposed NV-SRAM cell were confirmed.

Atomic Layer-by-Layer MOCVD of Complex Metal Oxides and In Situ Process Monitoring

The progress of atomic layer-by-layer metal-organic (MO) CVD of complex metal oxides and related growth technologies is reviewed. Atomic layer-by-layer MOCVD produces thin films of complex metal oxides that are of high crystalline quality, with a very smooth surface. These features allow us to fabricate modulated structures on an atomic scale, such as δ-doping, superlattice structure, and heterostructures. A common problem of oxide MOCVD is poor controllability of the growth conditions, mainly caused by instability of precursor supply. To overcome this problem, new precursors have been developed, and in situ process monitoring, using an ultrasonic transducer and spectroscopic ellipsometry, is applied during the MOCVD process. The reproducibility of MOCVD growth has been improved significantly.

Atomic layer-by-layer epitaxy of oxide superconductors by MOCVD

Abstract We have prepared thin films of c-axis oriented YBa2Cu3OX (YBCO) with a very smooth surface and roughness of less than a monomolecular layer of YBCO by atomic layer-by-layer metalorganic chemical vapor deposition on SrTiO3(100) and NdGaO3(110) substrates. A YBCO film with a large terrace width of 660 nm has been obtained on a NdGaO3(110) substrate. We have clarified the correlation between boulder formation and dislocations in the substrates by atomic force microscope observation. We have attempted to avoid producing boulder nuclei on dislocations exposed on the substrate surface by changing the usual sequence of source supply, Ba/Cu/Ba/Cu/Y/Cu, for 1 cycle into a new sequence, Ba/Ba/Y/Cu/Cu/Cu, and have successfully prevented the boulders. We also discuss issues of third generation precursors which are used in the liquid phase. We have also investigated hetero epitaxy of Sm2O3 ultrathin insulating films on YBCO thin films.

Nonvolatile flip-flop using pseudo-spin-transistor architecture and its power-gating applications

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-transistor architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved by its cell structure employing pseudo-spin-MOSFETs (PS-MOSFETs) that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized lowest BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and systems-on-chip (SoCs) using nonvolatile hierarchical-memory systems that are configured with NV-DFFs and nonvolatile static random access memories (NV-SRAMs).