Ryosho Nakane

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

High-Performance

We reveal that the MOVPE-based gas-phase doping can yield lower arsenic diffusion constant and lower leakage current n⁺/p junctions in Ge compared with conventional ion-implantation doping. Thus, the gas-phase doping is quite effective for realizing high-performance Ge n-channel MOSFETs. By using gas-phase doping for source/drain junction formation, the (100) GeO₂/Ge nMOSFETs have achieved high electron mobility of 1020 cm²/V·s while maintaining low junction leakage current and high I_on/I_off ratio of 10⁵. Furthermore, the (110) GeO₂/Ge nMOSFETs have also shown high electron mobility and high I_on/I_off ratio.

\hbox{GeO}_{2}/\hbox{Ge}

The authors developed a new analysis approach for evaluation of atomic ordering in full-Heusler alloys, which is extension of the commonly used Webster model. Our model can give accurate physical formalism for the degree of atomic ordering in the L21 structure, including correction with respect to the fully disordered A2 structure, i.e., the model can directly evaluate the degree of L21 ordering under a lower ordering structure than the complete B2-ordering structure. The proposed model was applied to full-Heusler Co2FeSi alloy thin films formed by rapid thermal annealing. The film formed at TA=800 °C showed a high degree of L21 ordering of 83% under a high degree of B2 ordering of 97%.

nMOSFETs With Source/Drain Junctions Formed by Gas-Phase Doping

We report that a Ni–InGaAs alloy can be used as a source/drain (S/D) metal for InGaAs metal–oxide–semiconductor field-effect transistors (MOSFETs), allowing us to employ the salicide-like self-align S/D formation. We also introduce Schottky barrier height (SBH) engineering process by increasing the indium content of InxGa1-xAs channels, which successfully reduces SBH down to zero. We propose a fabrication process for self-aligned metal S/D MOSFETs using Ni–InGaAs and demonstrate successful operation of the metal S/D InxGa1-xAs MOSFETs. The In0.7Ga0.3As MOSFETs exhibit an S/D resistance (RSD) that is 1/5 lower than that in P–N junction devices and a high peak mobility of 2000 cm2 V-1 s-1.

Analysis of L21-ordering in full-Heusler Co2FeSi alloy thin films formed by rapid thermal annealing

We have revealed that the MOVPE-based gas phase doping (GPD) can yield lower arsenic diffusion constant and lower leakage current n⁺/p junctions in Ge compared to conventional ion implantation doping. Thus, the GPD is quite effective for realizing high performance Ge n-channel MOSFETs. By using the GPD for source/drain (S/D) junction formation, the GeO<inf>2</inf>/Ge nMOSFETs have achieved high electron mobility of 804 cm²/Vs with maintaining low junction leakage current of 10⁻³ A/cm² and high I<inf>on</inf>/I<inf>off</inf> ratio of 10⁴.

Self-Aligned Metal Source/Drain InxGa1-xAs n-Metal–Oxide–Semiconductor Field-Effect Transistors Using Ni–InGaAs Alloy

We have found that GeO₂/Ge MOS structures fabricated by direct thermal oxidation yield significantly low interface trap density (D_it). Thus, Ge pMOSFETs using the GeO₂/Ge MOS structures with the superior interface properties have been fabricated for achieving high hole mobility and investigated for examining the impact of the interface properties on the device performance. Al₂O₃ or SiO films were employed for protecting the GeO₂/Ge MOS structures during the FET fabrication processes. The relationship between mobility and the fabrication conditions, such as the oxidation temperature, the annealing gas species, the substrate impurity concentration, the thickness of Al₂O₃ cap, and the surface orientation have been clarified.

High performance GeO 2 /Ge nMOSFETs with source/drain junctions formed by gas phase doping

In this paper, we have investigated the electron transport properties under two types of mobility enhancement engineering, which are channel strain and MOS interface buffer engineering. We have demonstrated epitaxial-based biaxially strained In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs. Tensile strained In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs shows high peak mobility of 2150 cm²/Vs. Furthermore, we have demonstrated high performance InAs-OI(-on insulator) MOSFETs on Si substrate with MOS interface buffer layer by direct wafer bonding, showing high peak mobility of 3180 cm²/Vs. The scattering mechanisms for the electron mobility in thin body In<inf>x</inf>Ga<inf>1−x</inf>As(InAs)-OI MOSFETs have been systematically analyzed and identified, for the first time.

Interface-controlled self-align source/drain Ge pMOSFETs using thermally-oxidized GeO 2 interfacial layers

The extremely thin body (ETB) InGaAs-on-insulator (-OI) metal–oxide–semiconductor field-effect transistors (MOSFETs) on Si substrates were demonstrated by using Ni–InGaAs alloy metal source/drain (S/D). It has been found that a light doping concentration of ~1016 cm-3 and indium-rich InGaAs channels (In0.7Ga0.3As) provide a high mobility of 1700 cm2 V-1 s-1 even in the channel thickness of 10 nm. This is the first demonstration of ETB III–V-OI MOSFETs combined with the metal S/D technology. We have also achieved excellent ID–VG characteristics with an Ion/Ioff ratio of over 105 and low SS of 120 mV/dec in 5-nm-thick In0.7Ga0.3As-OI MOSFETs.

Enhancement technologies and physical understanding of electron mobility in III–V n-MOSFETs with strain and MOS interface buffer engineering

We have investigated the effects of the tri-gate channel structure on electrical properties of extremely thin-body (ETB) InAs-on-insulator (-OI) MOSFETs. It was found that the tri-gate structure provides significant improvement in short channel effect (SCE) control even in ETB-OI MOSFETs by the simulation. We have fabricated and demonstrated tri-gate InAsOI MOSFETs with fin width of the top surface down to 40 nm. The tri-gate ETB InAs-OI MOSFETs shows better SCEs control with small effective mobility (μeff) reduction. Thus, we have demonstrated the operation of sub-20-nm-channel length (Lch) InAs-OI MOSFETs. The 20-nm-Lch InAs-OI MOSFETs show good electrostatic with subthreshold slope of 120 mV/decade and drain induced barrier lowering of 110 mV/V, and high transconductance (Gm) of 1.64 mS/μm. Furthermore, we have realized a wide-range threshold voltage (Vth) tunability in tri-gate InAs-OI MOSFETs through back bias voltage (VB) control.

High Performance Extremely Thin Body InGaAs-on-Insulator Metal?Oxide?Semiconductor Field-Effect Transistors on Si Substrates with Ni?InGaAs Metal Source/Drain

We report the operation of sub-60-nm deeply scaled InGaAs- and InAs-on-insulator (-OI) MOSFETs on Si substrates with MOS interface buffer engineering and Ni-InGaAs metal source/drain (S/D). InAs-OI MOSFETs provide 400% Ion enhancement, compared with an In0.53Ga0.47As control device with the same drain-induced-barrier-lowering (DIBL) of 100 mV/V, which is attributable to the mobility enhancement and the S/D parasitic resistance (RSD) reduction. In addition, InAs-OI MOSFETs with the MOS interface buffers show excellent electrostatic characteristics. InAs-OI MOSFETs with a channel length (Lch) of 55 nm shows small DIBL of 84 mV/V and subthreshold slope (S.S.) of 105 mV/dec, both of which do not significantly degrade with a decrease of Lch, thanks to the extremely thin channel thickness. In addition, from the simulation study, we have found that further vertical scaling and back biasing techniques can improve the control of short channel effect in InAs-OI MOSFETs.