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Dive into the research topics where Robert B. Richart is active.

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Featured researches published by Robert B. Richart.


IEEE Electron Device Letters | 1995

A convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection

C.-Y. Hu; D.L. Kencke; Sanjay K. Banerjee; Robert B. Richart; B. Bandyopadhyay; B. Moore; Effiong Ibok; Shyam Garg

A novel convergence scheme using substrate-bias-enhanced hot electron injection is proposed to tighten the cell threshold voltage distribution after erasure for stacked gate flash EEPROMs. By lowering the drain voltage and increasing the magnitude of the negative substrate bias voltage, the substrate current is reduced but the hot electron gate current is enhanced significantly, and the convergence time is shown to be more than a hundred times shorter than the previous scheme. With the convergence operation performed near the ON-OFF transition region of the cells, the total drain current for all the converged cells is reduced and low power consumption is achieved.<<ETX>>


IEEE Electron Device Letters | 1998

A multilevel approach toward quadrupling the density of flash memory

David L. Kencke; Robert B. Richart; Shyam Garg; Sanjay K. Banerjee

A multilevel scheme is presented that explores the possibility of quadrupling flash EEPROM storage density. Sixteen levels (4 bits/cell) of charge are stored in existing NOR stacked gate devices. A distinction is made between logical threshold voltages (as seen by the sense amplifier) and transistor threshold voltages (as defined by the gate characteristics), and precise programming gives distinct logical threshold voltage distributions, whereas transistor threshold voltage distributions are contained in a small 2.5 V range and kept low so that logical distributions survive a ten-year equivalent data retention bake.


Archive | 1996

Apparatus and method for multiple-level storage in non-volatile memories

Robert B. Richart; Shyam Garg


Archive | 1996

Electrically erasable reference cell for accurately determining threshold voltage of a non-volatile memory at a plurality of threshold voltage levels

Robert B. Richart; Shyam Garg


Archive | 1995

Non-volatile memory array with over-erase correction

Chung-You Hu; Robert B. Richart; Shyam Garg; Sanjay K. Banerjee


Archive | 1993

Method of making a MOS device with drain side channel implant

Robert B. Richart; Shyam Garg; Bradley T. Moore


Archive | 1993

Method of making a flash EPROM device utilizing a single masking step for etching and implanting source regions within the EPROM core and redundancy areas

Robert B. Richart; Shyam Garg; Fei Wang


Archive | 1995

Method for reading a non-volatile memory array

Robert B. Richart; Nipendra J. Patel; Shyam Garg


Archive | 1998

Post etch silicide formation using dielectric etchback after global planarization

Robert B. Richart; Shyam Garg


Archive | 1998

Method for selectively forming a silicide after a planarization step

Robert B. Richart; Shyam Garg

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Shyam Garg

Advanced Micro Devices

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Fei Wang

Advanced Micro Devices

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Sanjay K. Banerjee

University of Texas at Austin

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B. Moore

Advanced Micro Devices

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