Siang-Min Siao

New adaptable three-moduli set {2n+k, 2n-1, 2n-1-1} for residue number system-based finite impulse response implementation

This paper presents a new adaptable three-moduli set, f2n+k, 2n − 1, 2n−1 − 1g. It has three advantages for designing residue number system (RNS)-based digital signal processor (DSP) systems. First, it does not include a (2n + 1)-type modulo, thus providing a high-speed and low-cost system design. Second, three parallel DSP module channels achieve more efficient delay-balancing, thereby enhancing the system operation speed. Third, the set possesses an adaptable 2n+k modulo for avoiding over-ratio problems and reducing the system hardware overheads. Through the implementation of a mixed-radix conversion concept, an efficient converter was derived for the proposed adaptable moduli set. For system evaluation and comparison, the proposed adaptable and related moduli sets were used to implement a 16-tap RNS-based finite impulse response module that contains a forward converter, FIR module, and reverse converter. Based on TSMC 90-nm CMOS process technology, all implementations were synthesized to obtain layout results for a performance comparison. The design derived using the proposed moduli set achieved a 12%–46% AD2 (area × delay2) saving compared with those derived using other moduli sets or binary number systems.

High-performance reverse converter design for the new four-moduli Set {22n, 2n+1, 2n/2+1, 2n/2-1}

This paper presents a new four-moduli set {2²ⁿ, 2ⁿ +1, 2^n/2+1, 2^n/2-1} (where n is an even number) for meeting scale criteria. According to the new Chinese reminder theorem 1, the proposed moduli set can derive an efficient reverse conversion algorithm, and the converter architecture can then be designed. The proposed converter with a 32-bit width was implemented using the TSMC 90-nm complementary metal-oxide semiconductor process. The chip area is 980 × 920 μm² and the working frequency is 133 MHz. Savings of delay and power performance of more than 26.9% and 18.4%, respectively, are achieved using the proposed design.

Efficient reverse converter design for the new four-moduli set {22n, 2n + 1, 2n/2 + 1, 2n/2 – 1}

Abstract This paper presents a new four-moduli set {22n, 2n + 1, 2n/2 + 1, 2n/2 – 1} (n even). According to new Chinese remainder theorem 1, an efficient algorithm is derived for converting four residue numbers to binary. Then, the converter architecture is designed using shorter bit-width carry propagate adders to improve the hardware performance considerably. Compared with existing converters for related four-moduli sets, the proposed converter shows higher speed and lower power consumption. The proposed converter design with 64-bit width has been implemented on the basis of the Taiwan Semiconductor Manufacturing Company 90-nm CMOS process. The chip area is 1622 × 1657 μm2, and the working frequency is 116 MHz. The experimental results show that the proposed design achieves more than 26.9 and 18.4% savings in delay and power consumption, respectively. The converter also saves at least 39% in AD2 (area × delay2).

FPGA implementation for image object detection system on NoCs

This paper presents a routing approach for the mesh network on chip. This routing approach can choose the appropriate intermediate router to achieve the fast routing. It can balance the traffic load and achieve deadlock free. From the experimental results, our approach can improve at least 8.3% of the packet transmission latency comparing with the latest works. Next, the image object detection system, which includes 5 hardware intellectual properties and mesh network, is implemented in a FPGA platform. The total logic element is about 27,912, and the memory bits are 680,216. Its working frequency is 25 MHz such that it can process 22 frames per second for 320*240 image size.