Shyue-Wen Yang

An efficient VLSI design for a residue to binary converter for general balance moduli (2/sup n/-3,2/sup n/+1,2/sup n/-1,2/sup n/+3)

In this paper, we present a new four-moduli set (2/sup n/-3,2/sup n/+1,2/sup n/-1,2/sup n/+3) and an efficient residue to binary (R/B) converter design. The merits of the proposed four-moduli set include 1) larger dynamic range; 2) higher degree of parallelism for conversion; 3) balanced bit-width for internal RNS arithmetic operations; and 4) flexible moduli set selection. According to the relation between the proposed moduli, the divide-and-conquer technique is used to design a two-level converter architecture which has lower hardware cost and shorter critical delay. For the R/B converter designed with 12-b (n=3), our architecture has about 47% saving in hardware cost and 40% saving in critical delay compared to the last work.

VLSI architecture design for a fast parallel label assignment in binary image

We propose a new connected component labeling method based on a 3/spl times/4 window for a binary image. This method possesses parallel processing to achieve high speed operation. According to the proposed method, we design an efficient VLSI architecture which only uses two process elements and a class storage array to complete the whole label assignment after two raster scans. From experimental results, our design has better performance in terms of hardware cost and speed. This architecture has been verified on FPGA. It takes 6120 logic elements and its working frequency is about 80 MHz.

A High-Speed Network Interface Design for Packet-Based NoC

In this paper, we propose an interface design which supports serial-link packet-based transmission model for network-on-chip application The interface function consists of packet construction, flow control, error detect, re-transmission mechanism, data scrambler and 8b/10b transformation. The whole function is partitioned into three layers and designed as a peer-to-peer architecture. Every layer can be further divided into a transmitting portion that processes outbound traffic and a receiving portion that processes inbound traffic. We also simulate the buffer requirement with different transmission parameters. Finally, the layout area of network interface is about 0.43 mm2 based on 0.13 mum CMOS technology.

Parallel 3-Pixel Labeling Method and its Hardware Architecture Design

In this paper, we present a parallel connected component labeling method and its VLSI architecture design. The proposed method can assign labels to three pixels simultaneously for the raster scan input and then generate three label equivalences rapidly. We also present 3 arrays to process all label mergence. Based on the proposed method, we develop the hardware design for real-time application. The parallel architecture efficiently reduces total execution cycle significantly. From the experimental results, our 3-pixel labeling design can save 66% and 33% of the execution cycle comparing with the designs by 1-pixel labeling and 2-pixel labeling approaches, respectively.

Fast Fair Crossbar Scheduler for On-chip Router

This paper proposed a scheduling algorithm for a low-cost crossbar switch design in on-chip packet-switched micro-network. The scheduling algorithm is based on a distributed arbitration scheme over crossbar fabric. Each input port is designed with a mask circuit which can provide fair arbitration. As a result, our scheduler has lower power consumption because it does not need to toggle each node frequently. Experimental results show that designs utilizing our approach can reduce scheduling delay and hardware costs more than 43% and 49% respectively, as compared to those of the popular round robin algorithm. Based on the proposed scheme for 8-input scheduling circuit design, the critical delay is 0.98 ns and the power consumption is 98 muW with 50% traffic load at 100 MHz grant signal frequency in TSMC 0.18 mum technology

A micro-network on chip with 10-Gb/s transmission link

In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13μm CMOS technology. The core area of this chip is 990μm∗1600μm and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.

Extendable multi-pixel object labeling for digital image

This paper presents an extensible skew window for a multi-pixel inputs that enable parallel labeling. The corresponding 1 × 3 masks stack as a skew window based on the number of input pixels that require labeling. Based on the skew window and two pass processing, we developed a parallel labeling algorithm for assigning and merging parallel labels. To obtain tentative labels on the first pass, the priority-based label decision and parallel assignment are developed. On the second pass, parallel merging and replacement methods is proposed. From the experimental results this proposed design can perform object labeling at 30 f/sec for image up to 2560×2048 frame size.

Fast image foreground object segmentation based on block texture for embedded system implementation

In this paper, a novel block-based foreground object detection method based on block texture is presented. It can significantly reduce the memory usage when constructing the background model in dynamic scenes. The proposed background model and detection algorithm are suitable for implementing on embedded system platforms with resource limitations. The experimental results of processing benchmark videos show that our method has outcomes that are very close to ground truth segmentation. In addition, the proposed method requires approximately 23.97% less memory than the latest algorithms. Finally, the proposed approach is implemented on an embedded system platform. The processing speed can achieve a real-time rate of at least 20 fps, which is an improvement of 17.64% as compared to the latest algorithms.

Fast image moving object segmentation based on block texture for embedded system implementation

In this paper, we present a new moving object detection approach based on block texture. It can dramatically reduce the memory size when constructing the background model in a dynamic scene. The proposed background model and detection algorithm are suitable for implementing on embedded system platform which always has resource limitation. From the experimental results, our detection quality achieves 78% similarity in average. The memory consumption can be reduced 47.92% when comparing with the existing algorithms. Finally, the operation performance can be demonstrated on embedded system platform with 10 frames per second.

FPGA implementation for image object detection system on NoCs

This paper presents a routing approach for the mesh network on chip. This routing approach can choose the appropriate intermediate router to achieve the fast routing. It can balance the traffic load and achieve deadlock free. From the experimental results, our approach can improve at least 8.3% of the packet transmission latency comparing with the latest works. Next, the image object detection system, which includes 5 hardware intellectual properties and mesh network, is implemented in a FPGA platform. The total logic element is about 27,912, and the memory bits are 680,216. Its working frequency is 25 MHz such that it can process 22 frames per second for 320*240 image size.