Su-Hon Lin

An efficient VLSI design for a residue to binary converter for general balance moduli (2/sup n/-3,2/sup n/+1,2/sup n/-1,2/sup n/+3)

In this paper, we present a new four-moduli set (2/sup n/-3,2/sup n/+1,2/sup n/-1,2/sup n/+3) and an efficient residue to binary (R/B) converter design. The merits of the proposed four-moduli set include 1) larger dynamic range; 2) higher degree of parallelism for conversion; 3) balanced bit-width for internal RNS arithmetic operations; and 4) flexible moduli set selection. According to the relation between the proposed moduli, the divide-and-conquer technique is used to design a two-level converter architecture which has lower hardware cost and shorter critical delay. For the R/B converter designed with 12-b (n=3), our architecture has about 47% saving in hardware cost and 40% saving in critical delay compared to the last work.

VLSI Design of Diminished-One Modulo

The diminished-one modulo 2n+1 addition is an important arithmetic operation for a high-performance residue number system. In this paper, we propose a new circular-carry-selection (CCS) technique for modulo 2n+1 addition in the diminished-one number domain. The architecture design of CCS modular adder is simple and regular for various bit-width inputs. For actual VLSI implementation, the proposed modular adder can demonstrate its superiority of savings up to 39.5% in AreaxTime and 46.3% in TimexPower performances over those of the previous existing solutions under 180-nm CMOS technology. Finally, the chip area and the clock rate of CCS diminished-one modulo 216+1 adder are 26746 mum2 and 476 MHz, respectively.

2^{n}+1

In this paper, a systematic compensation approach is presented to efficiently design the approximate squaring function with a simple combinational logic circuit. Also, a set of recursive Boolean equations for general outputs is derived such that the logic circuit can be rapidly designed and reused for various bit-width inputs. In logic implementation, our design approach possesses less circuit cost and lower critical delay. Moreover, in error analysis, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are significantly improved by at least 26.95% and 61.59%, respectively, as compared with the existing approaches. Finally, a 7-bit approximate squaring function chip is accomplished to verify the circuit performance based on 0.6-/spl mu/m CMOS technology. The chip layout occupies 127/spl times/135 /spl mu/m/sup 2/ and the total number of transistors is 186.

Adder Using Circular Carry Selection

The moduli set (2n, 2n+1-1, 2n-1) which is free of (2n + 1)-type modulus is profitable to construct a high-performance residue number system (RNS). In this paper, we derive a reduced-complexity residue-to-binary conversion algorithm for the moduli set (2n, 2n+1-1, 2n-1) by using New Chinese Remainder Theorem (CRT). The resulting converter architecture mainly consists of simple adder and multiplexer (MUX) which is suitable to realize an efficient VLSI implementation. For the various dynamic range (DR) requirements, the experimental results show that the proposed converter can significantly achieve at least 23.3% average Area-Time (AT) saving when comparing with the latest designs. Based on UMC 0.18 μm CMOS cell-based technology, the chip area for 16-bit residue-to-binary converter is 931 × 931 μm2 and its working frequency is about 135 MHz including I/O pad.

Fast compensative design approach for the approximate squaring function

In this paper we propose a flexible 4-moduli set (2^p+k, 2^p+1, 2^p−1, 2^2p+1) which is profitable to construct a high-speed residue number system (RNS). We derive a simple reverse conversion algorithm for the proposed moduli set by using Chinese Remainder Theorem (CRT). The resulting converter architecture mainly consists of simple adders which are suitable to realize an efficient VLSI implementation. Based on TSMC 0.13um CMOS technology, the proposed reverse converter demonstrates its superiority in terms of area, delay and power over the converter design for the 4-moduli set (2ⁿ, 2ⁿ−1, 2ⁿ+1, 2²ⁿ+1) under the various dynamic range (DR) requirements. Finally, the chip area, the clock rate and the power consumption of the proposed 32-bit reverse RNS converter are 1227×1227um², 105MHz and 1.3mW respectively.

Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1-1, 2n-1)

A novel Hybrid-Carry-Selection (HCS) approach used for deriving an efficient modulo 2n-1 addition is presented in this study. Its resulting adder architecture which is mainly built by modified carry look-ahead adder (MCLA), carry prediction unit and simple multiplexer (MUX) is simple and regular for all n values. For VLSI implementation based on 180nm standard-cell technology, the HCS-based modulo 2n-1 adder demonstrates the superiority in AreaxTime (AT) performance over those of the latest existing solutions. The layout area and clock rate for HCS-based 216-1 modular adder chip are 25709 um2 and 518MHz respectively.

Efficient VLSI design of a reverse RNS converter for new flexible 4-moduli set (2 p+k , 2 p +1, 2 p −1, 2 2p +1)

The moduli set M1=(2n,2n+1-1,2n-1) which is free of 2a+1 modulus is profitable to construct a high-speed residue number system (RNS). In this paper, we derive a reduced-complexity residue-to-binary conversion algorithm for M1 by using new Chinese remainder theorem (CRT). The resulting converter architecture mainly consists of carry-save adders (CSAs), modular adders and multiplexer (MUX) which is suitable for an efficient VLSI implementation. Under the same dynamic range (DR) requirement, the proposed converter design is significantly more efficient than the latest design for M1 with respect to area-time (AT), time-power (TP) and area-time-power (ATP) products. Based on UMC 0.18 um CMOS cell-based technology, the chip area for 16-bit residue-to-binary converter is only 931times931um2 and the working frequency is 135 MHz.

Efficient VLSI Design of Modulo 2 n -1 Adder Using Hybrid Carry Selection

This paper presents a new 3-moduli set (2ⁿ-1, 2ⁿ+1, 2²ⁿ⁺¹) and its RNS reverse converter design. The proposed 3-moduli set supports 1) larger dynamic range and 2) shorter internal computing delay, comparing to the most popular modular set (2 ⁿ-1, 2ⁿ+1, 2ⁿ). Besides, to speed up residue to binary conversion, a low-cost hardware circuit is designed by only using two carry-save adders and one end around carry CLA (EACLA). Under the same dynamic range requirement, the proposed converter design is significantly more efficient than the latest design for modular set (2ⁿ-1, 2ⁿ+1, 2ⁿ) with respect to hardware cost and area-time product (AT). Based on UMC 0.18mum CMOS cell-based technology, the core area for 16-bit RNS reverse converter is only 1836mum² and the working frequency is 388MHz

Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2 n ,2 n+1 −1,2 n −1)

A new Hybrid-Carry-Selection (HCS) approach for deriving an efficient modulo 2n-1 addition is presented in this study. Its resulting adder architecture is simple and applicable for all n values. Based on 180-nm CMOS technology, the HCS-based modulo 2n-1 adder demonstrates its superiority in Area-Time (AT) performance over existing solutions.

Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2 n -1, 2 n +1, 2 2n+1 )

This paper proposes a novel arithmetic system called as Conjugate-Polynomial-Channel PRNS (CPCPRNS) which can efficiently perform N-point complex linear convolution with parallel version. Comparing with conventional PRNS-based technique, OUI system not only reduces the total computing complexity but also minimizes the size of modulus Q. Besides, CPCPRNS is suitable for VLSI hardware design. Based on 0.35~ CMOS cell library, it possesses average reduction of area and delay by 49% and 16% from the design experiences.