Siavoosh Payandeh Azad

Mixed-criticality NoC partitioning based on the NoCDepend dependability technique

The deployment of mixed-criticality applications on NoC (Network-on-Chip)-based MPSoC (Multiprocessor System-on-Chip) platforms requires a stringent protection of the communication and processing resources being utilized by hard-real-time parts of the the application in order to avoid interference of less critical application parts. In this contribution we present an approach for encapsulation of critical NoC communication resources, which guarantees no interference of non-critical data packets with critical communication data on the network. It is shown, how the NoC fault-tolerance technique “NoCDepend” can be used in order to achieve partitioning of a NoC into several criticality domains without additional overhead. The shape of the protected domains is arbitrary and the method can be applied to 2D and 3D NoCs.

SoCDep 2 : A framework for dependable task deployment on many-core systems under mixed-criticality constraints

In this paper, an open-source framework for task deployment of mixed-critical and non-critical applications under dependability constraints in Network-on-Chip (NoC) based systems is introduced. This system level design space exploration is guided by a System Health Monitoring Unit which keeps a holistic view of system health status. The framework supports task clustering, mapping and scheduling of different applications, using different heuristics, on a NoC-based architecture which can have different topologies. This enables exploration of 2D and 3D typologies, any turn model based routing algorithm, fault monitoring mechanisms and different fault models (Link, Turn, Node).

From online fault detection to fault management in Network-on-Chips: A ground-up approach

Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and the trend of integrating ever more components on a single chip, the Network-on-Chip (NoC) paradigm has emerged to address the scalability and performance shortcomings of bus-based interconnects. As the feature size shrinks, the system gets much more susceptible to faults caused by wear-out and environmental effects. Thus, in order to increase the reliability, creates the need for having mechanisms embedded into such a system that could detect and manage the faults in run-time. In this paper, a ground-up approach from fault detection to fault management for such a NoC-based system on chip is proposed that utilizes both local fault management for fast reaction to faults and a global fault management mechanisms for triggering a large-scale reconfiguration of the NoC. Also, detailed description of strategies for fault detection, localization, classification and propagation to a global fault management unit are provided and methods for local fault management are elaborated.

Customization methodology of a Coarse Grained Reconfigurable architecture

Mapping algorithms on CGRAs can lead to an inefficient implementation and hardware under-utilization if there is a mismatch between the granularity of reconfigurable processing unit and the algorithm. In this paper, we introduce a tool that takes the hardware configuration of a set of applications, identifies the unused parts of the CGRA, and let the user sweep the design space from fully programmable to fully customized by eliminating the unused components. User can select among multiple design points according to the application specification. This method is very useful to design multi-mode ASIC accelerators. The fully customized hardware generated using our tool has a negligible area and power overhead compared to the equivalent ASIC but can be generated significantly faster.

Logic-based implementation of fault-tolerant routing in 3D network-on-chips

The susceptibility of on-chip communication links and on-chip routers to faults has guided the research towards focusing on fault-tolerance aspects of 2D and 3D Network-on- Chips (NoCs). In this paper, we propose Logic-Based Distributed Routing for 3D NoCs (LBDR3D), a scalable, re-configurable and fault-tolerant mechanism, which utilizes only two virtual channels for implementing any deadlock-free turn model routing algorithm in partially vertically connected 3D NoCs. Such networks might emerge either due to the limitation of on-chip area for vertical links or due to occurrence of fault because of wear-out. LBDR3D guarantees live-lock freeness as well as connectivity regardless of the location and number of vertical links as long as faults do not disconnect the network. Our method relies on a limited set of bits which describe the topology and routing algorithm, updated using an offline algorithm. Our Experimental results show the comparison of LBDR3D with three previously proposed fault-tolerant mechanisms, Elevator-First, North-East To Z (NETZ) and East-Then-West (ETW). Compared to Elevator-First, our proposed mechanism is more flexible and in terms of packet latency, it performs better or equal under even extreme fault scenarios for vertical links. Furthermore, as long as the topology is supported by the routing algorithm, LBDR3D can tolerate faults on horizontal links in each layer. In contrast to NETZ and ETW, LBDR3D does not rely on the location of vertical links as long as the network is connected.

Digital system modeling and synthesis as an introduction to Computer Systems Engineering

This paper presents an overview of teaching hardware description languages (HDL) at Tallinn University of Technology (TUT). The structure of the course was modified by change of the approach to ground up learning through practical exercises. Different techniques to increase motivates of the students were introduced. These changes and their motivations are described in this paper. The course is taught as a first digital design modeling course for students who did not have prior digital design background. Observations and experiences from running the course over few years are described.

Fault-resilient NoC router with transparent resource allocation

The current trend of aggressive technology scaling results in a decrease in systems reliability. This motivates investigation of fault-resilient architectures which provide graceful degradation of systems functionality. In this paper, three novel fault-resilient Network-on-Chip (NoC) router architectures are proposed. These architectures, exploit the regularity of the router and reallocate available existing and spare units to maintain functionality of certain turns. The resource reallocation is performed transparently from systems resource manager and is based on predefined priorities. A new metric for architecture reliability comparison based on reliability block diagrams is introduced. In contrast to Silicone Protection Factor (SPF) metric, the proposed metric also takes into account the areas of different units. Area overhead and reliability of proposed architectures are compared with Triple Modular Redundancy (TMR) and Unit-Duplication mechanisms. All proposed architectures showed remarkable reliability improvement compared to original, TMR and Unit Duplication architectures; while at the same time, their area overhead is less than or equal to unit-duplication mechanisms.

High-level test generation for processing elements in many-core systems

The advent of many-core system-on-chips (SoC) will involve new scalable hardware/software mechanisms that can efficiently utilize the abundance of interconnected processing elements found in these SoCs. These trends will have a great impact on the strategies for testing the systems and improving their reliability by exploiting systems re-configurability to achieve graceful degradation of systems performance. We propose a strategy of Software-Based Self-Test (SBST) to be used for testing of processing elements in many-core systems with the goal to increase fault coverage and structuring the test routines in a way which makes test-data delivery in many-core systems more efficient. A new high-level fault model is introduced, which covers a broad class of gate-level Stuck-at-Faults (SAF), conditional SAF, and bridging faults of any multiplicity in processor control paths. Two algorithms for high-level simulation-based test generation for the control path and a bit-wise pseudo-exhaustive test approach for data path are proposed. No implementation details are needed for test data generation. A novel method for proving the redundancy of high-level functional faults is presented, which allows for precise evaluation of fault coverage.

Comprehensive performance and robustness analysis of 2D turn models for network-on-chips

Routing algorithms play an important role in Network-on-Chip (NoC) based System-on-Chips. Turn model based routing disallows some of the turns in order to avoid deadlock, while providing partial adaptivity. In this paper, all 2D uniform turn models are examined for deadlock freeness and connectivity; 50 deadlock free turn models are extracted that provide full connectivity in the network. An extended adaptivity metric is introduced to classify the turn models; all extracted turn models are compared in terms of adaptivity, robustness and latency. Experimental results identify the most robust turn models and the most efficient ones in terms of latency.

Automated area and coverage optimization of minimal latency checkers

With the scaling of silicon technology beyond the sub-micron domain, the probability of the system being exposed to different sources of faults increases. Manifestation of new defects during systems run-time, necessitates the need for a mechanism providing cost-effective online fault detection which performs concurrently with the circuits normal operation and has low area overhead and high fault coverage. Especially crucial is the fault detection latency, as the systems ability to isolate faults and recover from them is highly dependent on the detection time. This paper proposes two heuristics (branch-and-bound and greedy) for minimization of concurrent online checkers. Both algorithms use the concept of dominant checkers, proposed in this work. The method allows generating minimal area checkers satisfying a target fault coverage with the shortest possible fault detection latency. Experimental results demonstrate the area efficiency of the approach compared to other methods.