Jaan Raik

Test Configurations for Diagnosing Faulty Links in NoC Switches

The paper proposes a new concept of diagnosing faulty links in network-on-a-chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied for achieving near-100 per cent structural fault coverage for the network switches. The main novel contribution of this paper is to extend the use of test configurations for diagnosis purposes and to propose a method for locating faults in the NoC interconnection infrastructure. Additionally, a new concept of functional switch faults, called link faults, is introduced. The approach is well scalable (complexity is square root of the number of switches) and it is capable of unambiguously pinpointing the faulty links inside the switching network.

An External Test Approach for Network-on-a-Chip Switches

Over the past few years, network-on-a-chip (NoC) has become increasingly popular as a scalable interconnect infrastructure for IP cores. Simultaneously to developing new design paradigms, testing strategies for such network architectures have to be considered. The previous works on testing NoCs have been mainly based on general purpose design-for-testability (DFT) approaches and there is a lack of test algorithms dedicated to on-chip networks. The main contribution of this paper is a well-scalable external test method, where insertion of wrappers and scan paths will not be required. The paper proposes an external test method for NoC based on functional fault models, which targets single stuck-at faults in the network switches. Furthermore, 100 per cent of delay faults open and shorts between adjacent interconnection lines are covered by the method. The approach allows reaching higher fault coverage in comparison to the recent DFT based solutions

Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations

The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles, both, data and control parts of the design in a uniform manner is proposed. The method combines deterministic and simulation-based techniques. On the register-transfer level, deterministic path activation is combined with simulation based-techniques used for constraints solving. The gate-level local test patterns for components are randomly generated driven by high-level constraints and partial path activation solutions. Experiments show that high fault coverages for circuits with complex sequential structures can be achieved in a very short time by using this approach.

Parallel X-fault simulation with critical path tracing technique

In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults.

Turbo Tester: A CAD System for Teaching Digital Test

Traditional VLSI CAD/CAT systems for workstations are both costly and unable to handle large numbers of students simultaneously in educational courses. During recent years, many different low-cost tools running on PCs have been developed to fill this gap. They include the major basic tools for IC design: schematic capture, layout editors, simulators and place-and-route tools. However, low-cost systems for solving a wide class of tasks from the test domain, especially for teaching purposes, are missing.

Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips

The study proposes a new concept of test and diagnosis in regular mesh-like network-on-a-chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As it will be shown, such configurations can be applied for achieving near-100% structural fault coverage for the network switches. Additionally, a concept of functional switch faults, called link faults, is introduced. The approach is scalable (complexity grows linearly with respect to the number of switches) and it is capable of unambigously pinpointing the faulty links inside the switching network. Current paper also presents a set of design-for-testability (DfT) techniques for the application of test patterns from the external boundary of a NoC. The authors have implemented a parametrisable switching network and developed a set of DfT structures to support testing of network switches using external test configurations. The proposed structures include resource loopback for testing the crossbar multiplexer of the resource connection, a modification to the control part to force YX routing and a compact logic built-in self test (BIST) for the control unit. Experiments show that the proposed structures allow near-100% test coverage at the expense of less than 4% of extra switch area.

Sequential circuit test generation using decision diagram models

A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning and conformity test generation procedures. Structural faults in both, datapath and control part are targeted. High-level simplified and fast symbolic path activation strategy is combined with random local test pattern generation for functional units. The current approach has achieved high fault coverages for known sequential circuit benchmarks in a very short time.

Hierarchical defect-oriented fault simulation for digital circuits

A new fault model is developed for estimating the coverage of physical defects in digital circuits for given test sets. Based on this model, a new hierarchical defect oriented fault simulation method is proposed. At the higher level simulation we use the functional fault model, at the lower level we use the defect/fault relationships in the form of defect coverage table and the defect probabilities. A description and the experimental data are given about probabilistic analysis of a complex CMOS gate. Analysis of the quality of 100% stuck-at fault test sets for two benchmark circuits in covering physical defects like internal shorts, stuck-opens and stuck-ons. It has been shown that in the worst case a test with 100% stuck-at fault coverage may, have only 50% coverage for internal shorts in complex CMOS gates. It has been shown that classical test coverage calculation based on counting defects without taking into account the defect probabilities may lead to considerable overestimation of results.

Back-tracing and event-driven techniques in high-level simulation with decision diagrams

The paper addresses the problem of the cycle-based simulation performance of synchronous digital systems modeled by High-Level Decision Diagrams (DDs). A new class of DD representation, called Register-Oriented DDs (RODD) is introduced. The RODD model appears to be an efficient and compact representation of the system behavior for the high-level cycle simulation. In order to fully exploit the advantages of RODDs a new simulation algorithm, which is a combination of cycle-based forward event-driven and recursive back-tracing techniques is proposed. The characteristics of the simulation algorithms used to efficiently execute the evaluation of the DD network are discussed. Further the experimental results carried out on the real case examples demonstrating the gain in simulation performance of the proposed approach and a comparison of four cycle-based simulation algorithms are presented. Additionally, a comparison with the commercial event-driven and cycle-based HDL simulation tools is included.

Internet-Based Collaborative Test Generation with MOSCITO

This paper offers an Internet-based environment for enhancing problem-specific design flows with test pattern generation and fault simulation capabilities. Automatic Test Pattern Generation (ATPG) and fault simulation tools at structural and hierarchical levels available at geographically different places running under the virtual environment using the MOSCITO system are presented. These tools can be used separately, or in multiple applications, for test pattern generation of digital circuits. In order to link different tools together and with commercial design systems, respectively a set of translators was developed. The functionality of the integrated design and test system was verified by several benchmark circuits.