Raimund Ubar

Test synthesis with alternative graphs

Alternative graphs provide an efficient, uniform model describing the structure, functions, and faults in a wide class of digital circuits and for different representation levels. For test pattern generation, they provide a general theoretical basis for combining high-level approaches, symbolic techniques based on binary decision diagrams, and traditional topological algorithms.

Test cost minimization for hybrid BIST

This paper describes a hybrid BIST solution for testing systems-on-chip which combines pseudorandom test patterns with stored deterministic test patterns. A method is proposed to find the optimal balance between pseudorandom and stored test patterns to perform core test with minimum time and memory, without losing test quality. Two accurate algorithms are proposed for finding the optimal time-moment to stop pseudorandom test generation and to apply stored patterns. To speed up the optimization procedure, a method is proposed for fast estimation of the expected cost for different possible solutions with very low computational cost. Experimental results have demonstrated the feasibility of the proposed approach for cost optimization of hybrid BIST.

Test Configurations for Diagnosing Faulty Links in NoC Switches

The paper proposes a new concept of diagnosing faulty links in network-on-a-chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied for achieving near-100 per cent structural fault coverage for the network switches. The main novel contribution of this paper is to extend the use of test configurations for diagnosis purposes and to propose a method for locating faults in the NoC interconnection infrastructure. Additionally, a new concept of functional switch faults, called link faults, is introduced. The approach is well scalable (complexity is square root of the number of switches) and it is capable of unambiguously pinpointing the faulty links inside the switching network.

An External Test Approach for Network-on-a-Chip Switches

Over the past few years, network-on-a-chip (NoC) has become increasingly popular as a scalable interconnect infrastructure for IP cores. Simultaneously to developing new design paradigms, testing strategies for such network architectures have to be considered. The previous works on testing NoCs have been mainly based on general purpose design-for-testability (DFT) approaches and there is a lack of test algorithms dedicated to on-chip networks. The main contribution of this paper is a well-scalable external test method, where insertion of wrappers and scan paths will not be required. The paper proposes an external test method for NoC based on functional fault models, which targets single stuck-at faults in the network switches. Furthermore, 100 per cent of delay faults open and shorts between adjacent interconnection lines are covered by the method. The approach allows reaching higher fault coverage in comparison to the recent DFT based solutions

A hybrid BIST architecture and its optimization for SoC testing

This paper presents a hybrid BIST architecture and methods for optimizing it to test system-on-chip in a cost effective way. The proposed self-test architecture can be implemented either only in software or by using some test related hardware. In our approach we combine pseudorandom test patterns with stored deterministic test patterns to perform core test with minimum time and memory, without losing test quality. We propose two algorithms to calculate the cost of the rest process. To speed up the optimization procedure, a Tabu search based method is employed for finding the global cost minimum. Experimental results have demonstrated the feasibility and efficiency of the approach and the significant decreases in overall test cost.

Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations

The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles, both, data and control parts of the design in a uniform manner is proposed. The method combines deterministic and simulation-based techniques. On the register-transfer level, deterministic path activation is combined with simulation based-techniques used for constraints solving. The gate-level local test patterns for components are randomly generated driven by high-level constraints and partial path activation solutions. Experiments show that high fault coverages for circuits with complex sequential structures can be achieved in a very short time by using this approach.

Parallel X-fault simulation with critical path tracing technique

In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults.

Turbo Tester: A CAD System for Teaching Digital Test

Traditional VLSI CAD/CAT systems for workstations are both costly and unable to handle large numbers of students simultaneously in educational courses. During recent years, many different low-cost tools running on PCs have been developed to fill this gap. They include the major basic tools for IC design: schematic capture, layout editors, simulators and place-and-route tools. However, low-cost systems for solving a wide class of tasks from the test domain, especially for teaching purposes, are missing.

Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips

The study proposes a new concept of test and diagnosis in regular mesh-like network-on-a-chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As it will be shown, such configurations can be applied for achieving near-100% structural fault coverage for the network switches. Additionally, a concept of functional switch faults, called link faults, is introduced. The approach is scalable (complexity grows linearly with respect to the number of switches) and it is capable of unambigously pinpointing the faulty links inside the switching network. Current paper also presents a set of design-for-testability (DfT) techniques for the application of test patterns from the external boundary of a NoC. The authors have implemented a parametrisable switching network and developed a set of DfT structures to support testing of network switches using external test configurations. The proposed structures include resource loopback for testing the crossbar multiplexer of the resource connection, a modification to the control part to force YX routing and a compact logic built-in self test (BIST) for the control unit. Experiments show that the proposed structures allow near-100% test coverage at the expense of less than 4% of extra switch area.

Hybrid BIST time minimization for core-based systems with STUMPS architecture

This paper presents a solution to the test tone minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudo-random test patterns that are generated online, and deterministic test patterns that are generated offline and stored in the system. We propose a methodology to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.