Siddharth Gaba

Observation of conducting filament growth in nanoscale resistive memories

Nanoscale resistive switching devices, sometimes termed memristors, have recently generated significant interest for memory, logic and neuromorphic applications. Resistive switching effects in dielectric-based devices are normally assumed to be caused by conducting filament formation across the electrodes, but the nature of the filaments and their growth dynamics remain controversial. Here we report direct transmission electron microscopy imaging, and structural and compositional analysis of the nanoscale conducting filaments. Through systematic ex-situ and in-situ transmission electron microscopy studies on devices under different programming conditions, we found that the filament growth can be dominated by cation transport in the dielectric film. Unexpectedly, two different growth modes were observed for the first time in materials with different microstructures. Regardless of the growth direction, the narrowest region of the filament was found to be near the dielectric/inert-electrode interface in these devices, suggesting that this region deserves particular attention for continued device optimization.

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme.

Nanoscale resistive memory with intrinsic diode characteristics and long endurance

We report studies on nanoscale resistive memory devices that exhibit diodelike I-V characteristics at on-state with reverse bias current suppressed to below 10−13 A and rectifying ratio >106. The intrinsic diodelike characteristics are robust during device operation and can survive >108 write/erase programming cycles. The devices can be programmed at reduced programming voltages compared to earlier studies without the initial high-voltage forming process. Multibit storage capability was also reported. The intrinsic diode characteristics provide a possible solution to suppress crosstalk in high-density crossbar memory or logic arrays particularly for those based on bipolar resistive switches (memristors).

Si Memristive devices applied to memory and neuromorphic circuits

We report studies on nanoscale Si-based memristive devices for memory and neuromorphic applications. The devices are based on ion motion inside an insulating a-Si matrix. Digital devices show excellent performance metrics including scalability, speed, ON/OFF ratio, endurance and retention. High density non-volatile memory arrays based on a crossbar structure have been fabricated and tested. Devices inside a 1kb array can be individually addressed with excellent reproducibility and reliability. By adjusting the device and material structures, nanoscale analog memristor devices have also been demonstrated. The analog memristor devices exhibit incremental conductance changes that are controlled by the charge flown through the device. The performances of the digital and analog devices are thought to be determined by the formation of a dominant conducting filament and the continuous motion of a uniform conduction front, respectively.

Two-terminal resistive switches (memristors) for memory and logic applications

We review the recent progress on the development of two-terminal resistive devices (memristors). Devices based on solid-state electrolytes (e.g. a-Si) have been shown to possess a number of promising performance metrics such as yield, on/off ratio, switching speed, endurance and retention suitable for memory or reconfigurable circuit applications. In addition, devices with incremental resistance changes have been demonstrated and can be used to emulate synaptic functions in hardware based neuromorphic circuits. Device and SPICE modeling based on a properly chosen internal state variable have been carried out and will be useful for large-scale circuit simulations.

Device and SPICE modeling of RRAM devices

We report the development of physics based models for resistive random-access memory (RRAM) devices. The models are based on a generalized memristive system framework and can explain the dynamic resistive switching phenomena observed in a broad range of devices. Furthermore, by constructing a simple subcircuit, we can incorporate the device models into standard circuit simulators such as SPICE. The SPICE models can accurately capture the dynamic effects of the RRAM devices such as the apparent threshold effect, the voltage dependence of the switching time, and multi-level effects under complex circuit conditions. The device and SPICE models can also be readily expanded to include additional effects related to internal state changes, and will be valuable to help in the design and simulation of memory and logic circuits based on resistive switching devices.

Very Low-Programming-Current RRAM With Self-Rectifying Characteristics

To resolve the sneak leakage problem and reduce the power consumption in crossbar RRAM arrays, a Cu/Al2O3/aSi/Ta cell with self-rectifying characteristics is developed. The cell exhibits low operating current (~nA), high ON/OFF ratios (>100×), and pronounced nonlinearity. The use of low-programming-current RRAM elements avoids the current-driving capability bottleneck of selectors, while the integrated rectifying layer improves the RRAM operation reliability. Endurance of over 500 cycles with ~100 ON/OFF ratio was achieved without external current compliance. Even at such low programming levels, retention over 104 s at 100 °C can still be obtained.

Memristive Devices for Stochastic Computing

We show resistive switching effects in memristive devices exhibit significant stochasticity. When the switching is dominated by a single filament, the switching time is fully random and shows a broad distribution. However, the switching distribution can be predicted and responds well to controlled changes in the programming conditions. The native stochastic characteristic can be used to generate random bit streams with predictable biases that can lead to efficient and error-tolerant computing.

Ultralow Sub-1-nA operating current resistive memory with intrinsic non-linear characteristics

Sub-1-nA operating current conductive-bridge resistive memory devices showing pronounced rectifying behavior have been demonstrated in a cell structure consisting of Cu top electrode, atomic layer deposition Al2O3 switching film and polysilicon bottom electrode as an in-cell resistor. This ultralow current provides energy savings by minimizing write, erase, and read currents. Despite having such low currents, excellent retention, ON/OFF ratio, and endurance have been demonstrated. Devices programmed with <;1-nA peak current pass 6 h retention test at 85°C and show no significant degradation after 10000 write/erase cycles. Due to the partially formed filament, the devices at ON-state exhibit pronounced nonlinear I-V and current rectification-both factors are very beneficial for RRAM array operation. Multilevel storage can be obtained by controlling the filament shape through compliance current.

A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory

Recent advances in access-transistor-free memristive crossbars have demonstrated the potential of memristor arrays as high-density and ultra-low-power memory. However, with considerable variations in the write-time characteristics of individual memristors, conventional fixed-pulse write schemes cannot guarantee reliable completion of the write operations and waste significant amount of energy. We propose an adaptive write scheme that adaptively adjusts the write pulses to address such variations in memristive arrays, resulting in 7×--11× average energy saving in our case studies. Our scheme embeds an online monitor to detect the completion of a write operation and takes into account the parasitic effect of line-shared devices in access-transistor-free crossbars. This feature also helps shorten the test time of memory march algorithms by eliminating the need of a verifying read right after a write, which is commonly employed in the test sequences of march algorithms.