Kuk-Hwan Kim

Sub-5nm All-Around Gate FinFET for Ultimate Scaling

Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO2 shows an IDsat of 497muA/mum at VG=V D=1.0V. Characteristics of sub-5nm transistor are verified by using 3-D simulations as well as analytical models. A threshold voltage increases as the fin width reduces by quantum confinement effects. The threshold voltage shift was fitted to a theoretical model with consideration of the first-order perturbation theory. And a channel orientation effect, based on a current-flow direction, is shown

A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices

Silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8 nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N-and P-channel SiNAWI-FET showed the highest driving current on (110)/<110> crystal orientation without device rotation, whereas most 3-dimensional NMOS report higher driving current on 45deg device rotation rather than 0deg. Utilizing an 7 nm spherical nanowire on the 8 nm SiNAWI-NVM with ONO structure, 1.7 V VT-window was achieved from 12 V/80 musec program conditions with retention enhancement.

Doping-Free Nanoscale Complementary Carbon-Nanotube Field-Effect Transistors with DNA-Templated Molecular Lithography

This work was sponsored by the Samsung Electronics Co. Ltd. Dr. X.-J. Huang would like to express appreciation for the financial support of the Brain Korea 21 project, the School of Information Technology, and the Korea Advanced Institute of Science and Technology in 2007. Also this work was partially supported by the NRL program of the Korea Science and Engineering Foundation (KOSEF) grant funded by the Korea government (MEST) (no.R0A- 2007-000-20028-0).