Simon W.-B. Tam

Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary for Polycrystalline Silicon Thin-Film Transistors

A technique to extract trap states at the oxide-silicon interface and grain boundary has been developed for polycrystalline silicon thin-film transistors with large grains. From the capacitance–voltage characteristic, the oxide-silicon interface traps can be extracted. Potential and carrier density are also extracted. From the potential, carrier density, and current–voltage characteristic, the grain boundary traps can be extracted by considering the potential barrier at the grain boundary. Since these trap states are sequentially extracted, any shape of energy distribution of the trap states can be extracted. The correctness of this extraction technique is confirmed by comparison with two-dimensional device simulation.

Extraction of trap states in laser-crystallized polycrystalline-silicon thin-film transistors and analysis of degradation by self-heating

Trap states at the oxide-silicon interface and grain boundary in laser-crystallized polycrystalline-silicon thin-film transistors were extracted. The oxide-silicon interface traps and grain boundary traps can be extracted using the low-frequency capacitance–voltage characteristic and current–voltage characteristic, respectively. The traps above and below the midgap can be extracted using n-type and p-type transistors, respectively. The oxide-silicon interface traps consist of deep states and therefore seem to be caused by dangling bonds. The grain boundary traps consist of tail states and therefore seem to be caused by distortion of silicon-silicon bonds. Moreover, degradation by self-heating was analyzed. The oxide-silicon interface traps increase after the degradation. This means that silicon-hydrogen bonds are dissolved, and dangling bonds are generated. The grain boundary traps also increase a little.

Determination of the surface potential in thin-film transistors from C–V measurements

In this article we present a method for the determination of the gate voltage versus surface potential (VGS−ψS) relationship in thin-film transistors (TFTs), from low frequency capacitance–voltage (C–V) characteristics. This information is very important for device design, process characterization, and modeling of TFTs and provides the basis for extracting the gap density of states. The accuracy of the method is demonstrated by applying it to the analysis of C–V data generated by two-dimensional simulations. Its application to laser recrystallized polysilicon TFTs is presented.

Method for the determination of bulk and interface density of states in thin-film transistors

In this article we present a method for the accurate determination of interface and bulk density of states (DOS) in thin-film transistors (TFTs), based on the combined analysis of transfer (ID–VGS) and capacitance–voltage characteristics. This analysis has achieved a number of results, eliminating sources of inaccuracies that are known to be present in other methods. A procedure for the determination of the electron and hole flatband conductances and bulk Fermi energy is demonstrated. A recursive procedure is employed to extract the bulk DOS directly from Poisson’s equation. The advantages of this method are the greater immunity to noise from the original data, the use of the complete Fermi function (no 0 K approximation), and the applicability to thin active layers. This method yields the interface state density spectrum as well as the bulk DOS. This information is very important for device design, process characterization, and modeling of TFTs.

Extraction of Trap Densities at Front and Back Interfaces in Thin-Film Transistors

A technique for extracting trap densities at front and back interfaces has been developed for thin-film transistors. This extraction technique utilizes front and back capacitance-voltage characteristics, Q=CV, the Poisson equation and carrier density equations. The validity of this extraction technique is confirmed using device simulation. Actual trap densities are extracted, and it is found that both trap densities have the same figure. Moreover, they include deep states and therefore seem to be caused by dangling bonds.

51.4: Invited Paper: Modelling and Design of Polysilicon Drive Circuits for OLED Displays

Voltage input pixel driver circuits for low-temperature polysilicon thin-film transistor active-matrix organic light emitting diode displays have been designed to give uniform display brightness in the presence of spatial variation of threshold voltages. These pixel circuits are designed for a high-resolution and fine-grayscale display.

Analysis of plasma treatment and vapor heat treatment for thin-film transistors by extracting trap densities at front and back interfaces

Hydrogen (H) plasma treatment, oxygen (O) plasma treatment and water (H2O)-vapor heat treatment for polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) have been analyzed by separately extracting trap density at a front silicon-oxide interface (DF) and trap density at a back interface (DB). It is found that the H plasma treatment is apt to generate DF and DB. The O plasma treatment reduces DF, while the H2O-vapor heat treatment reduces both DF and DB. Improvement of transistor characteristics of poly-Si TFTs depends on understanding these results.

4.5: The Design and Driving of Active‐Matrix Electrochromic Displays Driven by LTPS TFTs

We have successfully driven a high-resolution (200dpi) QVGA active-matrix electro-chromic display (AMECD) with integrated driver electronics fabricated using low-temperature polysilicon thin-film transistor (LTPS-TFT) technology. This non-volatile reflective display requires low operating voltages, and possesses the advantages of high contrast ratio, sharp image quality, very large viewing angle and an image retention of a few days.

Poly-Si driving circuits for organic EL displays

In order to realize a fully integrated polycrystalline silicon thin-film transistor organic electro-luminescent display (poly-Si TFT-OELD) with good image quality, problems caused by spatially non-uniform device characteristic in TFTs must be addressed. In TFT-OELDs, spatial variation of threshold voltage in TFT driving circuits leads to non- uniform brightness and poor grayscale accuracy. Consequently, special pixel driver circuits are designed to overcome such difficulties. TFT-OELD analog and digital pixel driver circuits are closely examined and design difficulties are pointed out. For example, in an analog driver circuit, one difficulty is to minimize the power consumption given the spread of (Delta) V(Tau ); whereas in a digital driver circuit, one of the difficulties is how to maximize the number of grayscales. Performance of important circuits are analyzed and compared through circuit simulations using a poly-Si TFT model. Finally, suggestions of grayscale accuracy improvement are made.

Flexible microelectronics: New application for thin-film transistors in fingerprint sensors

— Thin-film transistors (TFTs) are field-effect transistors that can be used to create large-scale-integrated (LSI) circuits. The combination of high-performance TFTs and transfer technology of the TFTs has the potential to foster the rise of a new flexible microelectronics industry. This paper discusses the current status of flexible microelectronics, using a TFT fingerprint sensor (FPS) as an example. Technology used in active-matrix displays can easily be applied to the TFT FPS. TFT technology should not be confined to the display industry; its use should be expanded into the semiconductor industry. With the result presented in this paper, we declare a new era of flexible microelectronics open.