So Jeong Park

Scaling and Graphical Transport-Map Analysis of Ambipolar Schottky-Barrier Thin-Film Transistors Based on a Parallel Array of Si Nanowires

Si nanowire (Si-NW) based thin-film transistors (TFTs) have been considered as a promising candidate for next-generation flexible and wearable electronics as well as sensor applications with high performance. Here, we have fabricated ambipolar Schottky-barrier (SB) TFTs consisting of a parallel array of Si-NWs and performed an in-depth study related to their electrical performance and operation mechanism through several electrical parameters extracted from the channel length scaling based method. Especially, the newly suggested current-voltage (I-V) contour map clearly elucidates the unique operation mechanism of the ambipolar SB-TFTs, governed by Schottky-junction between NiSi2 and Si-NW. Further, it reveals for the first-time in SB based FETs the important internal electrostatic coupling between the channel and externally applied voltages. This work provides helpful information for the realization of practical circuits with ambipolar SB-TFTs that can be transferred to different substrate technologies and applications.

Controlled surface adsorption of fd filamentous phage by tuning of the pH and the functionalization of the surface

The surface adsorption of fd filamentous phage (fd phage) dispersed in different solution pHs was investigated with functionalized SiO2/Si substrates. The fd phages at high pH (∼9.0) were well-adsorbed on the SiO2/Si surface that was functionalized by 3-aminopropyltriethoxysilane, whereas those at low pH (∼3.0) were well-adsorbed on the cleaned SiO2/Si surface. The high affinity of the carboxylic acid groups (COO−) at high pH (∼9.0) was attributed to the fact that they give a higher adsorption to the positively charged amine groups (NH3+) on the surface of the substrate, similar to the effect of H3O+ at low pH (∼3.0) in a solution on the surface of the hydroxyl groups on the substrate (OH−). Interestingly, the aligned structures of the fd phage at intermediate pH (∼7.0), caused by the locally positively charged coat protein of the fd phage and the shear forces along the washing and blowing direction, were identified. The effective spring constant of the fd phage bundles was estimated to be 0.672 N/m using...

Flat-band voltage and low-field mobility analysis of junctionless transistors under low-temperature

This paper presents the low-temperature characteristics of flat-band (VFB) and low-field mobility in accumulation regime (μ0_acc) of n-type junctionless transistors (JLTs). To this end, split capacitance-to-voltage (C–V), dual gate coupling and low-temperature measurements were carried out to systematically investigate VFB. Additionally, the gate oxide capacitance per unit area Cox and the doping concentration ND were evaluated as well. Accounting for the position of VFB and the charge based analytical model of JLTs, bulk mobility (μB) and μ0_acc were separately extracted in volume and surface conduction regime, respectively. Finally, the role of neutral scattering defects was found the most limiting factor concerning the degradation of μB and μ0_acc with gate length in planar and tri-gate nanowire JLTs.

Channel access resistance effects on charge carrier mobility and low-frequency noise in a polymethyl methacrylate passivated SnO2 nanowire field-effect transistors

Channel access resistance (Rsd) effects on the charge carrier mobility (μ) and low-frequency noise (LFN) in a polymethyl-methacrylate (PMMA) passivated tin-oxide nanowire (SnO2-NW) field effect-transistor were investigated. To this end, the Y function method was employed for direct electrical parameters extraction without Rsd influence. Numerical simulation was used to evaluate gate-to-channel capacitance (Cgc) accounting for the electrostatic gate coupling effects through PMMA passivation layer. Furthermore, LFN measurements were carried out to study the SnO2/dielectrics interface. The carrier number fluctuation (CNF) noise model was found appropriate to interpret LFN data provided Rsd influence is included.

Low-temperature operation of junctionless nanowire transistors: Less surface roughness scattering effects and dominant scattering mechanisms

The less surface roughness scattering effects, owing to the unique operation principle, in junctionless nanowire transistors (JLT-NW) were shown by low-temperature characterization and 2D numerical simulation results. This feature could allow a better current drive under a high gate bias. In addition, the dominant scattering mechanisms in JLT-NW, with both a short (LM = 30 nm) and a long channel (LM = 10 μm), were investigated through an in-depth study of the temperature dependence of transconductance (gm) behavior and compared to conventional inversion-mode nanowire transistors.

Separation of surface accumulation and bulk neutral channel in junctionless transistors

The error rate of low-field mobility (μ0) extracted from the conventional Y-function method in junctionless transistors (JLTs) is found to be linearly proportional to the channel doping concentration (Nd) for a typical value of the first order mobility attenuation factor θ0 ≈ 0.1 V−1. Therefore, for a better understanding of their physical operation with higher accuracy, a methodology for the extraction of the low-field mobility of the surface accumulation channel (μ0_acc) and the bulk neutral channel mobility (μbulk) of JLTs is proposed based on their unique operation principle. Interestingly, it is found that the different temperature dependence between μ0_acc and μbulk is also confirming that the distribution of point defects along the channel in the heavily doped Si channel of JLTs was non-uniform.

Less mobility degradation induced by transverse electric-field in junctionless transistors

The mobility degradation by the relaxed electric-field in junctionless transistor (JLT) has been studied experimentally and theoretically. JLT showed less mobility degradation compared to the inversion-mode transistor in both planar-like and nanowire structures. The unique transconductance shape and the reduced degradation of the mobility in the nanowire JLT showed that it still has bulk neutral conduction portion in its total conduction while the immunity to the mobility degradation of JLT is enhanced with planar-structure. 2-dimensional numerical simulation confirmed the reduced transverse electric-field with bulk neutral conduction in JLT as well as the deviation of transconductance degradation by the channel doping concentration and the channel top width.

Soft-type trap-induced degradation of MoS2 field effect transistors

The practical applicability of electronic devices is largely determined by the reliability of field effect transistors (FETs), necessitating constant searches for new and better-performing semiconductors. We investigated the stress-induced degradation of MoS2 multilayer FETs, revealing a steady decrease of drain current by 56% from the initial value after 30 min. The drain current recovers to the initial state when the transistor is completely turned off, indicating the roles of soft-traps in the apparent degradation. The noise current power spectrum follows the model of carrier number fluctuation-correlated mobility fluctuation (CNF-CMF) regardless of stress time. However, the reduction of the drain current was well fitted to the increase of the trap density based on the CNF-CMF model, attributing the presence of the soft-type traps of dielectric oxides to the degradation of the MoS2 FETs.

Operation regimes and electrical transport of steep slope Schottky Si-FinFETs

In the quest for energy efficient circuits, considerable focus has been given to steep slope and polarity-controllable devices, targeting low supply voltages and reduction of transistor count. The recently proposed concept of the three-independent gated Si-FinFETs with Schottky-barriers (SBs) has proven to bring both functionalities even in a single device. However, the complex combination of transport properties including Schottky emission and weak impact ionization as well as the body effect makes the design of such devices challenging. In this work, we perform a deep electrical characterization analysis to visualize and decouple the different operation regimes and electrical properties of the SB Si-FinFETs using a graphical transport map. From these, we give important guidelines for the design of future devices.

In-depth electrical characterization of carrier transport in ambipolar Si-NW Schottky-barrier FETs

In this paper the operation mechanism of ambipolar Si-nanowire (Si-NW) Schottky-barrier (SB) FETs is discussed in detail using temperature dependent current-voltage (I-V) contour maps. Thermionic and field emission mechanism limited the overall conduction behavior of ambipolar Si-NW SB-FETs with considerable SB-height. However, Si-channel dominant transports with phonon scattering mechanism occur even in the SB based device at a specific bias condition, where charge carrier injection is saturated with a very thinned SB. Temperature dependent transconductance (gm) behavior, TCAD simulation and extracted activation energy (Eae) maps also support the explained operation principle of ambipolar Si-NW SB-FETs.