Sohaib Majzoub

Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm

In this paper, we propose a novel approach to voltage-island formation, for the energy optimization of many-core architectures, which mitigates the impact of process, voltage, and temperature (PVT) variations. The islands are created by balancing their shape constraints imposed by intra and inter-island communication with the desire to limit the spatial extent of each island to minimize PVT impact. In addition, to reduce the number of voltage levels in the design, we propose an efficient voltage selection approach that provides near optimal results, for a set of 33 examined cases, with more than a ten times speedup compared to the best-known previous methods. This run-time improvement is important, especially for large many-core platforms. Finally, we present an evaluation platform considering pre-fabrication and post-fabrication PVT scenarios where multiple applications with hundreds to thousands of tasks are mapped onto many-core platforms with hundreds to thousands of cores to evaluate the proposed techniques. Results show that the average energy savings for 33 test cases using the proposed methods are 37% compared to 16% obtained using previous methods.

PVT variation impact on voltage island formation in MPSoC design

On-chip process, voltage, and temperature (PVT) variations are projected to be a major bottleneck in deep submicron design. Such variations can change performance characteristics and push power budgets beyond their limits. In a voltage/frequency island (VFI) design, the initial VFIs determined using optimization without considering PVT may not be suitable after fabrication. This can lead to degradation in energy that largely offsets the advantage of using VFI. Thus, it is crucial to include PVT variations in any prefabrication energy optimization algorithm to improve the post-fabricaiton design quality. In this paper, we present a methodology that can reduce the differences by including PVT variations in the optimization. We analyze the PVT impact for different PVT characteristics and propose ways to handle the issue with a penalty of only 3%.

MorphoSys reconfigurable hardware for cryptography: the twofish case

This paper presents the mapping and performance analysis of the Twofish algorithm on MorphoSys. MorphoSys is a reconfigurable architecture that can provide high performance compared to custom hardware and yet preserves a level of flexibility compared to general-purpose processors. With today’s high demand for secure data transfer mediums including wired and wireless networks, there is a growing demand for real-time implementation of cryptographic algorithms. The choice of the Twofish algorithm, one of the five AES finalists, is because it is computationally intensive algorithm. It requires lookup tables, logical and arithmetic computations that stipulate high flexibility and performance. So it is a perfect algorithm to be mapped in order to evaluate such hardware.

Reconfigurable Platform Evaluation Through Application Mapping And Performance Analysis

The area of reconfigurable computing has received considerable interest in both its forms: the FPGA and coarse grain hardware. Since the field is still in its infancy, it is important to perform hardware analysis and evaluation of certain key applications on target reconfigurable architectures to identify potential limitations and improvements. This paper presents analysis of the advanced encryption standard (Rijndael), which is then implemented on a coarse grain reconfigurable platform (MorphoSys). We provide details of mapping Rijndael and present an analysis to highlight the apparent bottlenecks. We suggest methods of upgrading and enhancing the MorphoSys hardware accordingly

Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT

In this paper, we present a novel solution to the Voltage Selection Problem for large multi-core architectures. Compared to previous algorithms, ours provides similar results, but is more than 10x faster. This run-time improvement is important, especially for large multi-core platforms with hundreds of cores. We evaluate our algorithm in the context of a process, voltage, and temperature (PVT) variation-aware energy optimization framework.

Linear filtering using reconfigurable computing

Summary form only given. We present the mapping and performance analysis of a linear filtering algorithm on one of the reconfigurable computing (RC) prototypes, MorphoSys (M1) system. Mapping of a linear filtering algorithm, namely convolving a filter kernel across an image, onto this hardware is proposed. A performance analysis study is examined to evaluate the efficiency of the algorithm execution on the M1 RC system. For instance, an algorithm to convolve 8/spl times/8 image pixels with 3/spl times/3 filter kernel on the M1 8/spl times/8 RC array was run. Numerical examples were simulated to validate our results using the MorphoSys mULATE program, which simulates MorphoSys operations. Results showed that MorphoSys yielded a superior performance compared to the TMS320C40 DSP microprocessor.

Mapping and performance analysis of the Twofish algorithm on MorphoSys

Summary form only given, as follows. We present a mapping of Twofish encryption on the MorphoSys reconfigurable computer (RC) system that supports a high degree of parallelism through the 64-PE RC array integrated into the hardware design. This algorithm was chosen as it represents a promising cipher and is one of the five finalists for the Advanced Encryption Standards (AES). With todays growing needs of security on the Internet, there is an ever increasing demand for real-time implementation of cryptographic algorithms. Performance analysis of the Twofish algorithm mapping is also provided.

Reducing random-dopant fluctuation impact using footer transistors in many-core systems

Process variation creates core-speed discrepancy among the core in a many-core platforms. Random variation is one of the important components that contributes into core-speed discrepancy. In this paper, we propose a novel technique that uses footer transistors to reduce the impact of random process variation on delay and power in a many-core platform. Process variation is due to many fundamental deficiencies, impurities, and imperfections during the fabrication process at the nano-scale technologies. The results of this variation have a direct impact on two key parameters of the CMOS transistor: threshold voltage and gate length, which have major implication on the core speed and power. The random component of this variation is mostly attributed to the random-dopant fluctuation, which results in threshold voltage discrepancy among the cores. The proposed technique reduces the random dopant fluctuation by lowering the dopant density and then compensating the threshold voltage using a footer transistor. The results show a reduction of the total standard deviation from 25% down to 17% using the proposed method. Furthermore, the average energy saving of 30 different applications mapped on a many-core platform is improved by around 5%, and the performance by around 6%. The paper addresses the impact of process variation on core-speed in multi-cores.A new technique using multi-Vt is proposed to reduce RDF impact on delay and power.Our method lowers dopant density and then compensates Vt using a footer transistor.There was a 25-17% reduction in the total standard deviation of core-speed variation.Energy saving of 30 STG mapped on many-core improved by 5%, and performance by 6%.

Reducing random-dopant fluctuation impact on core-speed and power variability in many-core platforms

In this paper, we propose a novel technique that uses multi-Vt design to reduce the impact of random process variation on delay and power in a many-core platform. Random variation is mostly attributed to the random-dopant fluctuation. The proposed technique reduces this fluctuation by lowering the dopant density and then compensating the threshold voltage using a footer transistor. The results show a reduction of the total standard deviation from 25% down to 17% using the proposed method.

Instruction-Set Extension for Cryptographic Applications on Reconfigurable Platform

Recently, the area of reconfigurable computing has received considerable interest. Reconfigurable system is a specific name that is used for any machine that can be reconfigured during runtime to execute an algorithm as a hardware circuit. As a middle solution, reconfigurable systems stand halfway between traditional computing systems and specific hardware. This paper presents the mapping and performance analysis of two encryption algorithms, namely Rijndad and Twofish, on a coarse grain reconfigurable platform, namely MorphoSys. MorphoSys is a reconfigurable architecture targeted for multimedia applications. Since many cryptographic algorithms involve bitwise operations, bitwise instruction set extension was proposed to enhance the performance. The authors present the details of the mapping of the bitwise operations involved in the algorithms with thorough analysis. The methodology used can be utilized in other systems