Sommy Bounnak

200/spl deg/C, 96-nm wavelength range, continuous-wave lasing from unbonded GaAs MOVPE-grown vertical cavity surface-emitting lasers

We report record temperature and wavelength range attained using MOVPE-grown AlGaAs vertical cavity surface-emitting lasers (VCSELs). Unbonded continuous-wave lasing is achieved at temperatures up to 200/spl deg/C from these top-emitting VCSELs and operation over a 96-nm wavelength regime near 850 nm is also achieved from the same nominal design. Temperature and wavelength insensitive operation is also demonstrated; threshold current is controlled to within a factor of 2 (2.5-5 mA) for a wavelength range exceeding 50 nm and to within /spl plusmn/30% (5-10 mA) for a temperature range of 190/spl deg/C at 870 nm.<<ETX>>

Performance, uniformity, and yield of 850-nm VCSELs deposited by MOVPE

Vertical-cavity surface-emitting lasers (VCSELs) emitting near 850 nm and fabricated with the metal-organic vapor phase epitaxy (MOVPE) epitaxial growth technique and a planar proton implant process have been demonstrated with excellent performance, uniformity, and yield across a 3-in wafer. Four thousand lasers were tested on a three-inch-diameter wafer, with a yield of 99.8%. This translates into a yield of 94% for fully functional 34/spl times/1 arrays. The average threshold current, threshold voltage, and dynamic resistance at 10 mA operating current were 3.07 mA, 1.59 V, and 34 ohms, respectively. Uniformity of better than /spl plusmn/9% in threshold current, /spl plusmn/1% in threshold voltage, and /spl plusmn/1.5% in maximum optical output power across a 34-element array was demonstrated.

Vertical cavity surface emitting lasers for spaceborne photonic interconnects

Vertical cavity surface emitting lasers (VCSELs) offer substantial advantages in performance and simplicity of packaging over the edge emitting lasers currently being applied to state-of-the-art photonic interconnects. We have demonstrated operation of VCSELs at cryogenic temperatures and at temperatures as high as 200 degrees Celsius, with a single device operating from minus 55 degrees Celsius to plus 125 degrees Celsius. The devices operate to 14 GHZ and can be operated in excess of 1 GHZ with bias-free operation. Initial radiation tests indicate an order of magnitude improvement in hardness with respect to neutron damage over an LED which is currently used in spaceborne photonic interconnect modules. We also describe the packaging of VCSELs in compact multichip modules. By using passive alignment techniques, optoelectronic devices can be packaged in established multichip module fabrication schemes without adding costly high precision assembly techniques.

Cost Effective Optoelectronic Packaging for Multichip Modules and Backplane Level Optical Interconnects

Optical backplanes are of increasing interest for commercial and military avionic processors, and for commercial supercomputers. Projected interconnection density limits of electrical interconnects are rapidly becoming a bottleneck, preventing optimal exploitation of electronic processor capability. A potential obstacle to the commercial development of optoelectronic interconnect components for backplane-based systems is the small market for such specialized technology. In order to ensure that a cost effective solution is available for backplane based systems, commonality with a higher volume application is required. We describe optical packaging techniques for board level waveguides and multichip modules which exploit materials, processes and equipment already in widespread use in the electronics industry, and which can also be applied to a wide range of optoelectronic modules for local area network and telecommunications applications. Rugged polyetherimide waveguides with losses of 0.24 dB/cm have been integrated with conventional circuit board materials, and optoelectronic die have been packaged in a multichip module process using equipment normally used for purely electronic packaging. Practical optical interfaces and connectors have been demonstrated for board-to-backplane and board-to-multichip module applications, and offer increased pincount over their electrical counterparts while retaining compatibility with existing electrical connector alignment and fabrication tolerances.

FAST-Net optical interconnection prototype demonstration program

This paper reports progress toward the experimental demonstration of a smart pixel based optical interconnection prototype currently being developed under the Free-space Accelerator for Switching Terabit Networks (FAST-Net) project. The prototype system incorporates 2D arrays of monolithically integrated high- bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs). A key aspect of the FAST-Net concept is that all smart pixels are distributed across a single multi-chip plane. This plane is connected to itself via an optical system that consists of an array of matched lenses (one for each smart pixel chip position) and a mirror. The optical interconnect system implements a global point-to-point shuffle pattern. The interleaved 2D arrays of VCSELs and PDs in the prototype are arranged on a clustered self-similar grid pattern with a closest element pitch of 100 micrometers . The circular VCSEL elements have a diameter of 10 micrometers and the square PDs have an active region that is 50 micrometers wide. These arrays are packaged and mounted on circuit boards along with the CMOS driver, receiver, and FPGA controller chips. Micro-positioning mounts are used to effect alignment that is consistent with current MCM chip placement accuracy. Shuffled optical data links between the multiple ICs have been demonstrated in preliminary evaluation of this system. These results suggest that a multi-Terabit optically interconnected MCM module is feasible.

FAST-Net optical interconnection prototype demonstration

Highly interconnected multiprocessor systems are now performance limited by the backplane interconnection bottleneck associated with planar interconnection technologies. Smart pixel throughput capabilities are projected to exceed I Thitls/cm2 [1] and offer the promise of overcoming the bottlenecks of planar technologies for many types of interconnection-limited multiprocessor problems. Systems that use smart pixel-based free space optical interconnects (FSOI) provide two general dense interconnection capabilities: intelligent parallel data transfer and intelligent parallel data interchange. Optical imaging provides a high throughput approach to linking smart pixel planes for data transfer. In this case the high 110 density of smart pixels may provide a power consumption and size advantage over electronics [2,3]. For data interchange, FSOI provides the additional ability to perform the data partitioning and interleaving useful in space variant link interconnection patterns like the perfect shuffle (PS) [41,which are inherently difficult to implement in planar interconnection technologies. Such patterns are characterized by high BSBW [51. In multi-processor architecture design, there is a direct trade-off between minimum BSBW and latency in a network. It is therefore generally desirable to implement networks with the largest minimum BSBW that can be practically achieved to solve a given problem. The ability of optical elements to interconnect large arrays in space-variant patterns, without crosstalk in the medium, suggests that FSOI techniques are particularly promising for problems with high BSBW. For problems with greater than 1 ThitJsec BSBW (i.e., greater than the capabilities of a single chip) free space optical interconnects have a marked advantage [6,71. Therefore, globally interconnected multi-chip smart pixel based architectures have the potential to reap the full benefits of FSOI. This paper describes the experimental demonstration of a smart pixel based optical interconnection prototype currently being developed under the Free-space Accelerator for Switching Terabit tworks (FAST-Net) project, sponsored by the U.S. Defense Advanced Research Projects Agency. The prototype system incorporates 2-D arrays of monolithically integrated high-bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs). A key aspect of the FAST-Net concept is that all smart pixels are distributed across a single multi-chip plane. This plane is connected to itself via an optical system that consists of an array of matched lenses (one for each smart pixel chip position) and a mirror. The optical interconnect system implements a global point-to-point shuffle pattern. The interleaved 2-D arrays of VCSELs and PDs in the prototype are arranged on a clustered self-similar grid pattern with a closest element pitch of 100 tm. The circular VCSEL elements have a diameter of 10 pm and the square PDs have an active region that is 50 jim wide. These arrays are packaged and mounted on printed circuit boards along with CMOS driver, receiver, and FPGA controller chips. Micro-positioning mounts are used to effect alignment that is consistent with current MCM chip placement accuracy. Shuffled optical data links between the multiple ICs have been demonstrated in preliminary evaluation of this system. These results suggest that a multi-Terabit optically interconnected MCM module is feasible.

Polymer optical waveguide technology for multichip modules (MCMs) and board level interconnects

We have demonstrated a complete optical data between a pair of optical transmitter (Tx) and receiver (Rx) multichip modules (MCMs) using polymer optical waveguide array as interconnect media. The Tx and Rx MCMs each has three data channels and are fabricated using conventional MCM-C technology. The components used in our MCMs include Honeywells vertical cavity surface emitting lasers (VCSELs) at wavelength of 850 nm, and other commercial off-the-shelf Si devices such as Si detectors, laser drivers, and amplifiers. The waveguide interconnect is over 4-inch long, and includes both flexible ribbons and board integrated polymer waveguides with passively aligned connectors. The waveguides are finished with 45-degree mirrors at each end facets for interfacing with the VCSELs and the p-i-n detectors in the Tx and Rx modules, respectively. The loss of the overall optical link is less than 10 dB. We have measured a bit-error-rate of less than 10-12 at a data rate of 1 Gbps per channel.