Sonal Dey

Surface oxidation of the topological insulator Bi2Se3

An understanding of the aging and oxidation of the (0001) surface of Bi2Se3 is critical to a comprehensive physical picture of its topologically protected surface states. Here, the authors contribute new experimental observations about the aging and oxidation process. The authors find that surface aging in ambient conditions occurs in two major steps. Within 2 h of exfoliation, a series of ∼3.2 A high islands are observed by atomic force microscopy over approximately 10% of the surface. Subsequently, patch growth stops, and oxidation begins after the 2 h and continues until one quintuple layer has been oxidized. X-ray photoelectron spectroscopy shows no sign of oxidation before ∼120 min of exposure to air, and the oxygen 1 s peak, as well as oxidized Se 3d and Bi 4d peaks, are clearly present after ∼190 min of ambient exposure. Variable angle spectroscopic ellipsometry indicates that the oxidation of a full quintuple layer occurs on the time scale of days. These results are in good agreement with the time...

Role of Ge and Si substrates in higher-k tetragonal phase formation and interfacial properties in cyclical atomic layer deposition-anneal Hf1−xZrxO2/Al2O3 thin film stacks

Using a five-step atomic layer deposition (ALD)-anneal (DADA) process, with 20 ALD cycles of metalorganic precursors followed by 40 s of rapid thermal annealing at 1073 K, we have developed highly crystalline Hf1−xZrxO2 (0 ≤ x ≤ 1) thin films (<7 nm) on ∼1 nm ALD Al2O3 passivated Ge and Si substrates for applications in higher-k dielectric metal oxide semiconductor field effect transistors below 10 nm technology node. By applying synchrotron grazing incidence x-ray d-spacing maps, x-ray photoelectron spectroscopy (XPS), and angle-resolved XPS, we have identified a monoclinic to tetragonal phase transition with increasing ZrO2 content, elucidated the role of the Ge vs Si substrates in complete tetragonal phase formation (CTPF), and determined the interfacial characteristics of these technologically relevant films. The ZrO2 concentration required for CTPF is lower on Ge than on Si substrates (x ∼ 0.5 vs. x ∼ 0.86), which we attribute as arising from the growth of an ultra-thin layer of metal germanates betw...

Atomic layer deposited ultrathin metal nitride barrier layers for ruthenium interconnect applications

Resistance capacitance time delay in Cu interconnects is becoming a significant factor requiring further performance improvements in future nanoelectronic devices. Choice of alternate interconnect materials, for example, refractory metals, and subsequent integration with underlying barrier and liner layers are extremely challenging for the sub-10 nm nodes. The development of conformal deposition processes for alternate interconnects, liner, and barrier materials are crucial in order for implementation of a possible replacement for Cu interconnects for narrow line widths. In this study, the authors report on ultrathin (∼3 nm) chemical vapor deposition (CVD) grown ruthenium films on 0.5 and 1 nm thick metal nitride (TiN, TaN) barrier layers deposited via atomic layer deposition (ALD). Using scanning electron microscopy, the authors determined the effect of the underlying barrier layer on the coverage of the ruthenium overlayer. The authors utilized synchrotron x-ray diffraction with in situ rapid thermal an...

Mueller matrix spectroscopic ellipsometry based scatterometry simulations of Si and Si/SixGe1-x/Si/SixGe1-x/Si fins for sub-7nm node gate-all-around transistor metrology

In this paper, we report on Muller Matrix (MM) based scatterometry (aka. optical critical dimension or OCD) simulation strategies for two sub-7nm fin structures: one with a SixGe1-x/Si/SixGe1-x/Si/SixGe1-x/Si nanosheet structure and its comparison with a hypothetical Si-only fin structure of similar dimensions at sub-7nm semiconductor technology nodes. Si-fins are providing the performance improvements necessary for the transistors used in current generation integrated circuits. Development of sub-7nm technology nodes requires further performance improvements including advanced structures including new materials. This demand for improved performance has created the need for new fabrication processes such as extreme ultraviolet lithography, self-aligned quadruple patterning etc., along with new metrology challenges for adequately monitoring the semiconductor process control during fabrication of these advanced nanostructures.1 New materials and structures, such as, Si/Si1-xGex (0≤x≤1) stacked nanosheet structures have recently been developed as one of the potential replacement for Si-based FinFETs.2,3 We have simulated two fin structures: one with Si-fins and another with 3 alternating stacks of Si1-xGex/Si (x=0.3). We have used Rigorous Coupled Wave Approximation (RCWA) to simulate OCD spectra for 0° – 360° azimuthal angles in 10° steps by keeping the fin pitch fixed at 24nm while systematically changing (1) the fin critical dimension (CD) from 5.0–7.5nm in 0.5nm steps, (2) thickness of the Si and Si1-xGex (x=0.3) nanosheets (NST) from 8.0–1.5nm in 0.5nm steps, (3) the fin bending angle (FBA) from 0°–2.5° in 0.5° steps, and (4) the undercut angle (ED) of the Si1-xGex NSTs from 0°–10° in 2° steps. Difference in etch-rate of Si and Ge could give rise to non-zero ED during NST formation. Both the fin structures possess mirror symmetry about two orthogonal planes perpendicular to the substrate and with one of the planes along the fin long-axis. For angles 0°, 90°, 180°, and 270°, this mirror symmetry leads to absence of the cross-polarization terms in the simulated OCD spectra such that off-diagonal MM elements are zero over the simulated wavelength range. The broken mirror symmetry in other azimuthal angles leads to cross-polarization of the electrical field vectors which is seen in the off-diagonal MM elements becoming non-zero. Additionally, the off-diagonal MM elements show increased sensitivity and reduced correlation between the parameters under study which leads to a powerful metrology means for studying the critical fin-parameters for fast and reliable semiconductor process control in sub 7-nm technology nodes. All the non-zero MM-elements are found to be sensitive to changes in CD and NST with the off-diagonal elements showing greater sensitivity to the changes. At azimuthal angles <15°, MM23, MM31, and MM34 are highly sensitive to changes in etch undercut and fin bending angle defects. References: [1] D. Dixit et al., “Advanced applications of scatterometry based optical metrology,” Proc SPIE 10145, 101451H (2017). [2] N. Loubet et al., “Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET,” VLSI Technol. 2017 Symp., T230–T231, IEEE (2017). [3] R. Muthinti et al., “Advanced in-line optical metrology of sub-10nm structures for gate all around devices (GAA),” Proc SPIE 9778, 977810 (2016).