Songliang Jia

Low temperature Cu-Sn bonding by isothermal solidification technology

A low temperature wafer-to-wafer bonding technology for 3D packaging/integration based on Cu-Sn isothermal solidification (IS) technology is introduced in this paper. The fluxless bonding technique using Cu-Sn multilayer composites to produce higher re-melting temperature bonding layer is presented. The structure of the intermediate multilayers and bonding patterns are designed, and the bonding process is optimized. The microstructure of bonding layer was investigated by SEM (Scanning Electronic Microscopy) and EDS (Energy Dispersive X-Ray Spectrometer). The compositions of the bonding layer show that there are intermetallic compounds (IMCs) with higher melting points. The bonding layers consist of Cu6Sn5 and Cu3Sn phases. High strength of bonding layer has been detected, with average shear strength of 37.5MPa.

A study on packaging of PZT MEMS microphone

Packaging is the key issue in the commercialization of micromechanical microphone (also known as MEMS microphone). The ferroelectric-micromechanical microphone would have higher sensitivity and better acoustics performance. The microphones package will play a role in protecting the MEMS microphone chip, providing signal channel, shielding the electromagnetism interference from circumference as well. Furthermore, the acoustic performance of microphone is affected by package construction. The design and fabrication of a surface mount package for the PZT microphone is presented in this paper. The microphone chip and amplifier are integrated on an organic substrate, on which a metal cap is attached for EMI shielding. The sensitivity at 1kHz is -36.8dB (14.5mV/Pa) for packaged microphone. The selection of adhesives has been optimized to ensure enough shear strength and satisfied performance. Three types of adhesives were used for die attachment. Optical profiler was used to measure the surface topography of the PZT film before and after attachment. A comparison of failure modes after shear test, for different adhesives was made for materials selection. The acoustic performance affected by different configuration of the package has been investigated. The inlet hole on the cap can restrain the response at high frequency. Packaged microphones were evaluated after thermal cycling and thermal storage.

Electroless Plating Ni-based Barrier Layers for 3D Interconnection

Cu is the key material for both on-chip and inter-chip interconnections. It is the major interconnect material in packaging level, especially in through wafer electrical interconnection (TWEI). Barrier layer is necessary as Cu is easy to diffuse into Si, SiO₂ and other dielectrics. Comparing with traditional Ta and Ti based barrier layers, electroless plating NiMoP film has many advantages, such as seedless, low cost, lower resistivity, etc. Electroless plating NiMoP was investigated on SiO₂/Si. The plating solution was made up in house. Nickel sulfate and sodium molybdate were the sources of nickel and molybdenum. The effects of [MoO₄ ^2-]/[Ni²⁺] on the deposition rate of NiMoP and the film composition, electricity property, surface morphology & crystal structure were investigated. The deposition rate of NiMoP would be stable when the ratio of [MoO₄ ^2-]/[Ni²⁺] is higher than 0.08. The atom percentage of Mo in NiMoP film increases with the increasing of [MoO₄ ^2-]/[Ni²⁺]initially and then reaches a saturation amount at about 10 at%, while the concentration of P decreases with the increasing [MoO₄ ^2-]/[Ni²⁺]. The resistivity of NiMoP film can be as low as 70.2 muOmegacm. The optimized deposition condition for a low resistivity NiMoP barrier is with the pH value of 9.0-10.0, plating temperature in the range of 85-90degC and [MoO₄ ^2-]/[Ni²⁺]of around 0.043. With Auger analysis, the deposited NiMoP film can be the effective diffusion barrier layers after 400degC annealing. A demonstration of 3D interconnection with electroless NiMoP barrier layer has been fabricated.

The impact of zincation on the electroless nickel UBM for low cost flip chip technology

Electroless nickel on aluminum bondpads followed by solder bumping is regarded as one of the promising solutions of low cost flip chip technology. Zincation is a key process step to form a strong, electrical conductive connection between nickel and aluminum. The morphology of the bondpad changes slightly after the degreasing and oxide removal procedures. Large zinc grains grow during zincation. To get more uniform and smooth zinc films, a second zincation is applied. The newly deposited zinc film leads to better adhesion of the flip chip interconnection. Therefore double zincation is employed instead of single zincation. The change of the surface roughness corresponds well with its morphology. The surface of the bondpad is examined by SEM and AFM. Another key factor of the zincation procedure is the immersion time in the bath. And in this paper the immersion time for the first and second zincations is 45 and 15s respectively. For a properly prepared nickel UBM on an 80/spl mu/m/spl times/80/spl mu/m Al bondpad followed by a eutectic SnPb solder bump (250/spl mu/m in diameter), its shear strength is as high as 150 MPa and the electrical resistance of a bump is as low as 0.05/spl Omega/.

Tin bumping for wafer level lead-free packaging

A pure tin bumping technology is described in this paper. TiW/Cu was used as under bump metallurgy. The pure tin was electroplated and formed solder bumps by reflow. The height of the solder bump is about 50 micron. SEM was used for observing the microstructure of interface, and the EDAX was used for investigating the composition of the intermetallic compounds. Tin and copper interreacted with each other to form intermetallic compounds, Cu/sub 6/Sn/sub 5/. Shear tests and thermal aging were used for evaluation of the tin solder bumps. The pure tin bumps were stored at 150/spl deg/C for 1, 4, 9 and 16 days respectively. The composition of intermetallic compound changed as time going on. After several days of thermal aging, C/sub 3/Sn formed between Cu and Cu/sub 6/Sn/sub 5/. The total thickness of intermetallic compound increased after thermal aging. The relationship between the thickness of intermetallic compound and the square root of aging time is linearity, implying that the growth of the IMC layer was diffusion controlled. Comparing the strength of tin solder bumps before and even after thermal aging, it was found that after 16 days of thermal aging, the shear strength of solder bump did not change obviously.

Evaluation of the Thermal Resistance of CSOP24 Ceramic Package

On the basis of MIL STD 883 method 1012 and SEMI standard G30-88 and G32-86. purely electrical approaches were implemented to measure the thermal resistance of CSOP24 package. Firstly the temperature sensitive parameter (TSP) was measured and calibrated in a temperature controlled fluid trough. Then proper test conditions including measurement current (IM) and test power PHmiddot were chosen according to experiments. Thermal resistance measurements were carried out in the two conditions: radiator with big heat sink which keeps the case temperature Tc at 60 degC. and temperature controlled fluid trough. In addition, two kinds of thermal test chips with different size (1.91times1.91mm and 3.92times3.92mm) were used to test the influence of the chip size. Experimental result was provided. Moreover, the thermal resistance of the CSOP24 package was simulated by utilizing Fluent software.

Lead Profile Optimization and Stress Analysis for Hermetic Metal Package

Glass seal is commonly utilized in hermetic metal package to assure hermeticity and protect electronic devices. However large stresses may exist in glass seal and induce failure or cracks. To reduce stresses, lead profile is optimized and stepped leads are utilized in metal packages of TO-254A. Stresses in glass seals were simulated and investigated using ANSYS. Simulation results showed that maximum tensile stress and maximum compression stress for packages with stepped leads are about 1~3% of that of packages with conventional leads. Furthermore, lead integrity experiments were carried out and simulation results were validated. Lead integrity experiments showed that no cracks were found in metal packages with stepped leads but failure occurred in other metal packages with conventional leads. And seal tests indicated that measured leak rate of packages with stepped leads was quite low, smaller than 1 x 10-3 Pa cm3 /s, while the leakage rate was about (2.0 ~ 6.0) x 10-2 Pa cm3 /s for metal packages with conventional leads. Both simulation and experimental results demonstrate that stepped leads are critical to reduce stresses and enhance the reliability of hermetic metal packages.

Design and control of horizontal extension for gold bumping

Gold bump is commonly used for COG (chip on glass) packaging of LCD driver. The market of Au bump COG is growing fast. Mostly, the gold bumping is finished on the whole wafer, following the process of UBM sputtering, thick photoresist patterning, electric gold plating, etc. Gold bumps with 10/spl sim/30 /spl mu/m in height, 45/spl sim/70 /spl mu/m in pitch and 15/spl sim/25 /spl mu/m in space have been fabricated. Horizontal extension should be controlled during bumping. Design and process optimization have been done to get high quality Au bumps.

Simulation and optimization of solution flow in fountain-plating cup for Au bumping

A fountain-plating cup is designed and fabricated in IMETU (Institute of Microelectronics, Tsinghua University). The simulation and optimization of solution flow in the cup by computational fluid dynamics (CFD) tool have been introduced in this paper. The structure of the plating cup is presented and the position, the thickness and the hole size of the diffuser and the velocity of flow at entrance are used as the parameters for simulation. With the results of the simulation, Au bumps with tolerance in /spl plusmn/2.5 /spl mu/m on a 6 inch wafer have been fabricated.

Au-Ag bonding for 3D stacked package

Bipolar transistor is widely applied in the field of power electronics. However, there still exist many difficulties to manufacture high voltage Bipolar transistor nowadays. One of the approaches that can improve the withstand voltage of the Bipolar transistor is to stack multiple low-withstand voltage bipolar chips. SiC Schottky diode is bipolar transistor with aluminum electrode as anode and silver electrode as cathode. The purpose of this work was to realize the 3D die stacking by Au-Ag thermocompression bonding of two chips with the same electrode structure as SiC Schottky Diode. Gold stud bumps were made on the aluminum electrode by thermosonic bonding. Two chips were stacked together by Au-Ag thermocompression bonding. Different bonding parameters and annealing conditions were evaluated. Experiment results showed that increasing bonding temperature or annealing duration could improve the bonding quality. The Au-Ag bonding with 15N bond load at 250°C for 20 minutes followed by nitrogen annealing at 160°C for 30 minutes exhibited a successful bonding performance. The Au-Ag bonding interface was analyzed by SEM (scanning electron microscope) and EDX (energy dispersive x-ray spectroscope). Continuous alloy compositions were observed by atomic diffusion between gold and silver.