Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Shuidi Wang is active.

Publication


Featured researches published by Shuidi Wang.


Journal of Asian Natural Products Research | 2007

The metabolites of a mangrove endophytic fungus, Penicillium thomi

Guo-Qiang Chen; Yongfa Zhu; Hui Wang; Shuidi Wang; Ruifeng Zhang

The chemical constituents research of the fermentation of Penicillium thomi separated from the root of Bruguiera gymnorrhiza led to the isolation of a new compound, 4′,5-dihydroxy-2,3-dimethoxy-4-(hydroxypropyl)-biphenyl (1) and 11 known compounds. The structures of isolated compounds were determined by spectroscopic and chemical analysis. Their cytotoxic effects against three human cancer cell lines (A549, HepG2 and HT29) were also investigated.


international conference on electronic packaging technology | 2009

Low temperature Cu-Sn bonding by isothermal solidification technology

Yibo Rong; Jian Cai; Shuidi Wang; Songliang Jia

A low temperature wafer-to-wafer bonding technology for 3D packaging/integration based on Cu-Sn isothermal solidification (IS) technology is introduced in this paper. The fluxless bonding technique using Cu-Sn multilayer composites to produce higher re-melting temperature bonding layer is presented. The structure of the intermediate multilayers and bonding patterns are designed, and the bonding process is optimized. The microstructure of bonding layer was investigated by SEM (Scanning Electronic Microscopy) and EDS (Energy Dispersive X-Ray Spectrometer). The compositions of the bonding layer show that there are intermetallic compounds (IMCs) with higher melting points. The bonding layers consist of Cu6Sn5 and Cu3Sn phases. High strength of bonding layer has been detected, with average shear strength of 37.5MPa.


electronic components and technology conference | 2005

A study on packaging of PZT MEMS microphone

Jian Cai; Haining Wang; Shuidi Wang; Xiaoming Wu; Tian-Ling Ren; Songliang Jia

Packaging is the key issue in the commercialization of micromechanical microphone (also known as MEMS microphone). The ferroelectric-micromechanical microphone would have higher sensitivity and better acoustics performance. The microphones package will play a role in protecting the MEMS microphone chip, providing signal channel, shielding the electromagnetism interference from circumference as well. Furthermore, the acoustic performance of microphone is affected by package construction. The design and fabrication of a surface mount package for the PZT microphone is presented in this paper. The microphone chip and amplifier are integrated on an organic substrate, on which a metal cap is attached for EMI shielding. The sensitivity at 1kHz is -36.8dB (14.5mV/Pa) for packaged microphone. The selection of adhesives has been optimized to ensure enough shear strength and satisfied performance. Three types of adhesives were used for die attachment. Optical profiler was used to measure the surface topography of the PZT film before and after attachment. A comparison of failure modes after shear test, for different adhesives was made for materials selection. The acoustic performance affected by different configuration of the package has been investigated. The inlet hole on the cap can restrain the response at high frequency. Packaged microphones were evaluated after thermal cycling and thermal storage.


international electron devices meeting | 2004

Novel ferroelectrics-based micro-acoustic devices and their ultrasonic applications

Yiping Zhu; Tian-Ling Ren; Yi Yang; Xiaoming Wu; Ning-Xin Zhang; Litian Liu; Zhimin Tan; Haining Wang; Jian Cai; Shuidi Wang; Zhi-Jian Li

Novel ferroelectric thin film based micro-acoustic devices have been designed and fabricated using silicon based micro-machining process. These devices have excellent performance, miniature size and high reliability, and could be compatible with conventional integrated circuit process. And more important, they can be both used as microphone and microspeaker. The micro-acoustic devices could find wide and novel application in practical ultrasonic systems.


Tsinghua Science & Technology | 2011

Development of a BGA package based on Si interposer with through silicon via

Hao Zhang; Jian Cai; Qian Wang; Tao Wang; Shuidi Wang

A ball grid array (BGA) package based on Si interposer with through silicon via (TSV) was designed. Thermal behaviors of the designed BGA with Si interposer has been analyzed and compared to a conventional BGA with BT substrate in the approach of finite element modeling (FEM). The Si interposer with TSV was then fabricated and the designed BGA package was demonstrated. The designed BGA package includes a 100 μm thick Si interposer, which has redistribution copper traces on both sides. Through vias with 25 to 40 μm diameter were fabricated on the Si interposer using deep reactive ion etching (DRIE), plasma enhanced chemical vapor deposition (PECVD), copper electroplating and chemical mechanical polishing (CMP), etc. TSV in the designed interposer is used as electrical interconnections and cooling channels. 5 mm by 5 mm and 10 mm by 10 mm thermal chips were assembled on the Si interposer.


international conference on electronic packaging technology | 2005

Through wafer via technology for 3-D packaging

Guoqiang Feng; Xiao Peng; Jian Cai; Shuidi Wang

Through wafer via fabrication has been one of the key technologies for 3-D packaging and microsystem packaging. Four different through wafer via fabrication technologies and applications are reviewed, such as laser drilling, deep reactive ion etching (DRIE), photo assisted electro chemical etching (PAECE) and KOH etching. Especially, KOH etching is widely used in bulk micromachining of microelectromechanical system (MEMS) fabrication and featured with anisotropic etching of silicon. Through wafer via technology based on double-sided KOH etching is presented, which needs double-sided alignment exposure. A SiO/sub 2/ layer is deposited by PECVD for insulation layer and then TiW/Cu sputtering and Cu electroplating are used to deposit conductive layers. In order to reroute the metal layer of silicon wafer with vias, photosensitive dry film and liquid photoresist exposure are tested.


international conference on electronic packaging technology | 2005

Microstructure of AuSn Wafer Bonding for RF-MEMS Packaging

Jian Cai; Qian Wang; XiaoGang Li; Woon-bae Kim; Shuidi Wang; Jun-Sik Hwang; Chang-youl Moon

RF-MEMS is one of the most potential applications for MEMS products. Eutectic solder wafer bonding is one of the attractive methods for RF-MEMS wafer level packaging. A process of gold-tin hermetical wafer bonding was developed in SAIT, Korean. Different UBM systems and thin films of gold-tin were deposited on cap wafer, RF-MEMS device wafer and substrate wafer (if needed). The bonding was performed in N2 ambience with pressure. The cross section of bonding layer had been studied using SEM/EDAX. The thickness of bonding layer is uniform, ranging from 5mum to 7mum. Pretreatment is important to obtain good adhesion and successful microstructure. Voids could be detected without ashing. Optimal process, such as plasma cleaning, would eliminate these voids. There existed different regions in the bonding layer due to inter-diffusion between Au-Sn and other elements. Different intermetallic formed at the bonding layer. The compositions of the intermetallic was identified by EDAX and analyzed according to the Au-Sn phase diagram. The microstructures of the bonding layer are similar for different bonding temperatures in experiments, which indicates lower bonding temperature can get the same hermetical sealing. Typically, there are Au rich layer, AuSn IMC layer and Sn/Au-Ni-Ti layer in the bonding layer between cap wafer and substrate wafer, while there are Au layer, Au-Sn-Ni compound layer in the bonding layer between device wafer and substrate wafer. From the EDAX analysis, different intermetallic compound (IMC) can be identified as AuSn2, AuSn and other composition. Hermetical and shear strength test were performed for as-bonded dice. The test results indicated there is little difference among different bonding process. Fracture surfaces after shear test were investigated as well. The fracture was inside Au-Sn IMC. It indicates the UBM selected is suitable for application. Reliability test was also performed


international conference on electronic packaging technology | 2010

Properties of TiN films deposited by atomic layer deposition for through silicon via applications

Wenjie Zhang; Jian Cai; Dejun Wang; Qian Wang; Shuidi Wang

TiN diffusion barrier layers were deposited on SiO2/Si substrate by ALD method that employed TiCl4 and NH3 as the source and reactant gases, respectively, at a temperature range between 350°C and 500°C. Properties of films, including deposition rate, resistivity, surface roughness and chemical composition, were investigated, and performance of TiN diffusion barrier layer was also verified. Deposition rate of TiN films is almost a constant (∼0.15Å/cycle), independent from the process condition, measured by ellipsometer and verified by AES. This demonstrates TiN films were grown by ALD growth mechanism. Resistivity of the films is below 125µΩ·cm when deposition temperature is above 400°C,which is very low compared to TiN film grown by other CVD methods, and it decreases with the increase of reaction temperature and TiN films thickness. AFM analysis result reveals that RMS roughness is low (∼0.636nm). Chemical composition was analyzed by AES and XPS, content of chorine in TiN films is about 0.5 at. %, and the ratio of N and Ti by atomic concentration is nearly 1:1. In order to research the performance of TiN as diffusion barrier layer, copper is sputtered on TiN films and then post-annealed in a vacuum ambient of 10−5 Pa at 400°C for 1h. AES analysis results indicate that no copper diffusion into the SiO2 for Si with Cu/TiN/SiO2 films after annealing.


international conference on electronic materials and packaging | 2006

Electroless Plating Ni-based Barrier Layers for 3D Interconnection

Jian Cai; Guoqiang Feng; Zhigang Yang; Shuidi Wang; Songliang Jia

Cu is the key material for both on-chip and inter-chip interconnections. It is the major interconnect material in packaging level, especially in through wafer electrical interconnection (TWEI). Barrier layer is necessary as Cu is easy to diffuse into Si, SiO<sub>2</sub> and other dielectrics. Comparing with traditional Ta and Ti based barrier layers, electroless plating NiMoP film has many advantages, such as seedless, low cost, lower resistivity, etc. Electroless plating NiMoP was investigated on SiO<sub>2</sub>/Si. The plating solution was made up in house. Nickel sulfate and sodium molybdate were the sources of nickel and molybdenum. The effects of [MoO<sub>4</sub> <sup>2-</sup>]/[Ni<sup>2+</sup>] on the deposition rate of NiMoP and the film composition, electricity property, surface morphology & crystal structure were investigated. The deposition rate of NiMoP would be stable when the ratio of [MoO<sub>4</sub> <sup>2-</sup>]/[Ni<sup>2+</sup>] is higher than 0.08. The atom percentage of Mo in NiMoP film increases with the increasing of [MoO<sub>4</sub> <sup>2-</sup>]/[Ni<sup>2+</sup>]initially and then reaches a saturation amount at about 10 at%, while the concentration of P decreases with the increasing [MoO<sub>4</sub> <sup>2-</sup>]/[Ni<sup>2+</sup>]. The resistivity of NiMoP film can be as low as 70.2 muOmegacm. The optimized deposition condition for a low resistivity NiMoP barrier is with the pH value of 9.0-10.0, plating temperature in the range of 85-90degC and [MoO<sub>4</sub> <sup>2-</sup>]/[Ni<sup>2+</sup>]of around 0.043. With Auger analysis, the deposited NiMoP film can be the effective diffusion barrier layers after 400degC annealing. A demonstration of 3D interconnection with electroless NiMoP barrier layer has been fabricated.


international conference on electronic packaging technology | 2005

The impact of zincation on the electroless nickel UBM for low cost flip chip technology

Yu Yang; Jian Cai; Shuidi Wang; Songliang Jia

Electroless nickel on aluminum bondpads followed by solder bumping is regarded as one of the promising solutions of low cost flip chip technology. Zincation is a key process step to form a strong, electrical conductive connection between nickel and aluminum. The morphology of the bondpad changes slightly after the degreasing and oxide removal procedures. Large zinc grains grow during zincation. To get more uniform and smooth zinc films, a second zincation is applied. The newly deposited zinc film leads to better adhesion of the flip chip interconnection. Therefore double zincation is employed instead of single zincation. The change of the surface roughness corresponds well with its morphology. The surface of the bondpad is examined by SEM and AFM. Another key factor of the zincation procedure is the immersion time in the bath. And in this paper the immersion time for the first and second zincations is 45 and 15s respectively. For a properly prepared nickel UBM on an 80/spl mu/m/spl times/80/spl mu/m Al bondpad followed by a eutectic SnPb solder bump (250/spl mu/m in diameter), its shear strength is as high as 150 MPa and the electrical resistance of a bump is as low as 0.05/spl Omega/.

Collaboration


Dive into the Shuidi Wang's collaboration.

Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Researchain Logo
Decentralizing Knowledge