Young-Jae Min

A CMOS TDC-based digital magnetic Hall sensor using the self temperature compensation

A CMOS TDC-based digital magnetic Hall sensor using the self temperature compensation schemes is proposed. The proposed sensor consists of the sensor device, its bias and signal-processing circuit which is fully compatible with a standard CMOS technology. For the high magnetic sensitivity, the MAGFET is implemented with proper geometric parameters. The TDC-based digital circuit is proposed for the low power consumption and easy design. The self temperature compensation schemes of mobility and threshold voltage temperature effects are utilized for the low temperature variation. The proposed sensor is implemented with a standard 0.18 mum CMOS technology and shows the good detectable resolution by 0.8 muT under magnetic fields ranging from 0 to 0.8 T and temperature variations by 250 nT ranging from -40degC to +80degC. And the very low power consumption by 360 muW at 1.8 V supply voltage is measured.

Two-stage digital I/Q demodulator employing a reconfigurable 16-phase down-mixing technique

This letter presents a new two-stage digital I/Q demodulator employing a reconfigurable 16-phase quadrature intermediate frequency (IF) sampling technique for multistandard wireless systems such as mobile TV applications. The proposed two-stage digital I/Q demodulator provides the flexibility for the multiphase scheme such as a quadrature phase shift keying (QPSK) and 16-quadrature amplitude modulation (QAM) at the level of down-mixing, which introduces an efficient architecture for the following decimation filter. In this letter, the prototype chip has been implemented in a 0.18µm standard CMOS technology and occupied with the active chip area of 0.02mm2. The power consumption of the fabricated chip is 0.42mW with a 1.8V supply voltage at the sampling frequency of 26 MHz. The experimental results show that the proposed two-stage digital I/Q demodulator is suitable for multistandard wireless systems which require small silicon area and low power dissipation.

A 2.5-V 4-μW Low-Power Delta-Sigma Modulator for Implantable Cardiac Pacemaker with Periodic Bias Current Reduction Technique

This paper proposes a 2.5 V supply, 4 μW low-power delta-sigma modulator for implantable cardiac pacemaker system. Periodic bias current reduction technique is proposed to reduce the power consumption of delta-sigma modulator implemented with switched-capacitor integrator. 2nd order delta-sigma modulator exploiting MOSFETs operating in moderate inversion region is fabricated in a CMOS 0.25 μm process. Measurement results of delta-sigma converter show a power dissipation of 4 μW, and 46 dB of peak SNR in a 128 Hz signal bandwidth.

A unified DLL-controlled active rectifier in 6.78 MHz resonant-coupling wireless power receivers for space-limited portable and wearable applications

An active rectifier in 6.78MHz resonant-coupling wireless power receivers for space-limited portable and wearable applications is presented. To improve the power efficiency and reduce the die area, a fully NMOS transistor-based active rectifier with a unified delay-locked loop (DLL) controller is proposed. The proposed rectifier has been implemented in a 0.35μm CMOS technology with a die area of 0.612mm2. The measured peak and minimum power efficiency within the power range of 80mw to 440mW are 91.8% and 69.6%, respectively.

An all-digital duty-cycle and phase-skew correction circuit for QDR DRAMs

A compact all-digital duty-cycle and phase-skew correction circuit for quadrature data rate interface-based DRAM applications is presented. To improve the correction time, this work adopts a successive approximation register controller for both duty-cycle and phase-skew correction. The proposed correction circuit has been fabricated in a 65 nm CMOS technology with a die area of 0.086mm2. The duty-cycle and phase-skew of 4-phase outputs are corrected with 56 cycles. The measured duty-cycle error and phase-skew are below 21% and 25 ps, respectively.

Sub-1 V V-I converter-based voltage-controlled oscillator with a linear gain characteristic

This letter proposes a novel sub-1V voltage-current (V-I ) converter-based voltage-controlled oscillator (VCO) for the low-voltage phaselocked loop (PLL) of display driver integrated circuit. The proposed VCO improves on the state-of-the-art V-I converter-based VCO, which uses a firstorder current equation for the VCO, to achieve linear voltage-to-frequency gain of the VCO (KVCO) over the full range of the control voltage, from the ground to the supply voltage in sub-1V CMOS technology. To obtain a full supply transition output with high immunity to noise, the improved VCO is designed to control the gate voltage of a metal-oxide-semiconductor fieldeffect transistor (MOSFET), instead of the supply voltage of a ring oscillator without significant area overhead. As a result, the proposed VCO obtains a linear KVCO with a wider control voltage range than a conventional VCO when its tuning range is from 1.25 to 3.6GHz in a 65 nm 1.0V CMOS technology.

Adaptive Vector Filtering with Low Computational Complexity for Image Sensor Applications

In this paper, a new adaptive vector filtering method with low computational complexity for image sensor applications is presented. The alternation between the ASDDF and the AVMF in the dependence on the order-statistics theory reduces the computational complexity. In addition, the proposed method provides excellent detection of noisy pixels and removes both chromatic and achromatic noisy pixels.