Soon-Kwon Lim

Ink-jet printing of cu-ag-based highly conductive tracks on a transparent substrate.

We have developed a Cu-Ag-based mixed metal conductive ink from which highly conductive tracks form on a flexible substrate after annealing at low temperature. Addition of small Ag particles significantly improves the particle packing density by filling the interstices formed between the larger Cu particles, which in turn facilitates better conductivity compared to pure Cu metal film. The particle size and volume ratio of the Ag particles added should be carefully controlled to achieve maximum packing density in the bimodal particle system, which is consistent with the theoretical considerations of the Furnas model. In addition, we demonstrate direct writing of complex patterns that exhibit high conductivity upon annealing at sufficiently low temperature (175-210 degrees C) to not damage the transparent plastic substrate such as polyethersulphone (PES).

PECVD‐based nanocrystalline‐silicon TFT backplanes for large‐sized AMOLED displays

— A 14.1-in. AMOLED display using nanocrystalline silicon (nc-Si) TFTs has been developed. Nanocrystalline silicon was deposited using conventional 13.56-MHz plasma-enhanced chemical vapor deposition (PECVD). Detailed thin-film characterization of nc-Si films was followed by development of nc-Si TFTs, which demonstrate a field-effect mobility of about 0.6–1.0 cm2/V-sec. The nc-Si TFTs show no significant shift in threshold voltage when over 700 hours of constant current stress is applied, indicating a stable TFT backplane. The nc-Si TFTs were successfully integrated into a 14.1-in. AMOLED display. The display shows no significant current decrease in the driving TFT of the 2T-1cap circuit because the TFTs are highly stable. In addition to the improved lifetime of AMOLED displays, the development of nc-Si TFTs using a conventional 13.56-MHz PECVD system offers considerable cost advantages over other laser and non-laser polysilicon-TFT technologies for large-sized AMOLEDs.

70.4: A 14.1inch AMOLED Display using Highly Stable PECVD based Microcrystalline Silicon TFT Backplane

We have developed a 14.1 inch AMOLED display using microcrystalline silicon (mc-Si) TFTs. Microcrystalline silicon was deposited using conventional 13.56MHz Plasma Enhanced Chemical Vapor Deposition (PECVD). Detailed thin film characterization of mc-Si films was followed by development of mc-Si TFTs which show a field effect mobility of around 0.7∼1.0cm2/V.s. The mc-Si TFTs show no significant shift in threshold voltage when applied with a long time constant current stress, indicating a stable TFT backplane. The mc-Si TFTs were successfully integrated in a 14.1 inch AMOLED display. The display shows no significant current decrease in the driving TFT of the 2T circuit, even after long time of lifetime tests. Along with improved lifetime for AMOLED display, the development of mc-Si TFTs using conventional 13.56 MHz PECVD system offers significant cost advantages over other laser or non-laser polysilicon TFT technologies for AMOLED.

Bistable switching of twist direction in a twisted-nematic liquid crystal cell

We propose a bistable liquid crystal mode based on switching of the twist direction in a conventional π/2-twisted nematic cell. Switching between the −π/2 and +π/2 twist states can be performed by applying vertical and/or in-plane electric fields. The proposed bistable mode has an infinite memory time because the two stable twist states have the same elastic free energy.

Effects of illumination wavelength on the accuracy of optical overlay metrology

As the integration density in the manufacturing of ICs increases and tighter design rules are implemented, the accuracy of overlay in the photolithography process is becoming all the more important. Consequently, investigation and characterization of the accuracy (as well as precision) of the overlay measurement are being required to insure that the overlay metrology tool qualifies for the new technologies. In this paper, we analyze the relationship between wafer substrate types and the respective characteristic overlay measurement errors associated with them. We compare results using different illumination wavelengths in the overlay tool. We define the Wafer Induced Shift (WIS) contribution to the measurement accuracy error and introduce a metric for it. And we analyze the relationship between the TIS and WIS. We show that the wavelength of the optical overlay measurement (OL, for short) should be fitted separately to each of the various kinds of overlay measurement targets, or marks. Buried type targets, covered by transparent materials, for which the measurement is made through the transparent interlayer, benefit from wavelength selection due to the possible improvement in contrast associated with an interference effect. Open type targets, on the other hand, in which the measurement signal is collected off the substrate shape itself, do not benefit from that. There is another problem to consider, however. Such targets may show a considerable WIS, even thought TIS and precision are good both before and after etch. The WIS error can be as high as 100 nm. This could create serious OL problem and it means that TIS and precision are not enough to characterize the quality of measurement, and WIS is equally important, it not more so. We look into the causes of WIS in the substrate shape, overlay mark design and fabrication method. We show that with careful selection of illumination wavelength, some layers produce no WIS. On the other layers WIS remains a problem and other methods are still required to control it.

Stress behavior of CVD-PSG Films Depending on Deposition Methods and Hillock Suppression

In multilevel metallization processes, stress induced void and hillock formations cause serious problems with respect to the reliability of metal line, such as pitting corrosion of metal during the pad etching step, mask misalignment due to surface roughness, and open or short failure of metal line. It is generally known that these types of metal-film related problems are due to stress relaxation process in the metal line stress-induced by thermal expansion mismatch between metal and over/underlayer oxide film or compressive stress of overlayered passivation dielectric film. In this study, the stress behavior of phosphosilicate glass (PSG) film on the Al-l%Si film, deposited by different CVD methods, is investigated. Here we found that the degree of PSG film stress is related with the suppression of hillock growth, void formation, and cracking of passivation layer, depending on the heat treatment and heat treatment. Using stress measurement, surface profilometer, and SEM, the relation between passivated PSG film stress on metal line and the metal line failures is analyzed. In addition, an effective method of hillock suppression is suggested, which is the use of PECVD-PSG film on the metal line before heat treatment of 400°C or that of any type of PSG film before 350°C.

Fabrication of an all‐layer‐printed TFT‐LCD device via large‐area UV imprinting lithography

Abstract Nanoimprint lithography (NIL) using ultraviolet (UV) rays is a technique in which unconventional lithographic patterns are formed on a substrate by curing a suitable liquid resist in contact with a transparent patterned mold, then releasing the freshly patterned material. Here, various solutions are introduced to achieve sufficient overlay accuracy and to overcome the technical challenges in resist patterning via UV imprinting. Moreover, resist patterning of all the layers in TFT and of the BM layer in CF was carried out using UV imprinting lithography to come up with a 12.1‐inch TFT‐LCD panel with a resolution of 1280×800 lines (125 ppi).

49.1: Fabrication of 23” PVA LCD Panel by Laser Ablation Process of ITO

We fabricated the world first 23” PVA LCD panel of which transparent electrode (ITO) was patterned by “laser ablation process”. Generally photo process is used to pattern the transparent electrode. To simplify this photo process we tried to develop laser ablation process to pattern the ITO. Current photo process is composed of 6 steps such as Coating the Photoresist, Baking, Exposure, Development, Etching, and Stripping. But we succeeded in simplifying this process by the laser ablation process. From this experiment, we could identify the possibility of laser ablation process which can be used on the patterning process of transparent electrodes.

P-10: Mechanism of Lowering Contact Resistance between Transparent Conducting Oxide Layer and Mo/Al/Mo Layer in TFT-LCDs

It was found that the mechanism of lowering contact resistance between TCO and Mo/Al/Mo layer is the side ring contact between TCO and top Mo of Mo/Al/Mo. This is contrary to the previous results that used MoxAly interfacial layer to explain the low contact resistance of TCO and Mo/Al/Mo layer.

Optimization of boron doped polysilicon resistors

This paper is concerned with an optimized process of boron doped polysilicon resistors. First, we propose process conditions that make grain size bigger in order to minimize the ratio of grain boundary that results in the variation of polysilicon resistance. Second, we propose process conditions that sustain safe structure at continuous heat treatment processes, electrical and temperature characteristics.