Mona M. Eissa

Challenges and Rewards of Low-Abrasive Copper CMP: Evaluation and Integration for Single-Damascene Cu/Low-k Interconnects for the 90nm Node

Low-abrasive content slurries for copper (Cu) chemical-mechanical planarization (CMP) have been developed to achieve removal rate and removal uniformity comparable to conventional slurries. They can improve post-CMP defectivity, improve topography and allow operation at lower polish pressures that are more compatible with the low-dielectric constant (low-k) materials required for current and future high-performance interconnects. Integration of these slurries into a yielding product with 9-level Cu/low-k metallization requires fundamental learning and process characterization. This paper discusses the some of the challenges encountered during development, integration, and qualification of a low-abrasive Cu CMP process for Texas Instruments (TI) Incorporateds 90 nm technology node with copper/organosilicate interconnect. As abrasive content is reduced, the slurry chemistry must play a larger role in CMP removal. A more aggressive reactive chemical formulation requires an effective inhibitive component to keep Cu static etch rate low. As a result, wafer-scale process and consumable interactions, die-scale planarization efficiency, and feature-scale removal rates each become more sensitive to process changes. Pressure and temperature have larger effects on removal rate/profile than conventional slurries, and complete clearing of Cu puddled over underlying topography becomes more difficult. Successful integration of these slurries, however, can achieve excellent results in dishing and erosion topography, Cu thickness uniformity, and Cu loss in small features such as vias and landing pads. Low-abrasive content solutions are also more stable and easy to handle in slurry distribution vessels and lines, have lower scratch and residue defectivity, and have greatly extended margin for overpolish. As lowabrasive content Cu slurry options continue to evolve to become manufacturable solutions, their benefits far outweigh the costs and challenges encountered in their successful integration.

Fabrication and Performance of Integrated Fluxgate for Current Sensing Applications

The recently developed Fluxgate technology from Texas Instruments has enabled the production of the industry’s first current sensing integrated circuit with a fully integrated fluxgate device and a compensation coil driver. This paper presents an overview of the Fluxgate technology, focusing on the fabrication and performance of the integrated magnetic field sensing device.

Polymers for high performance interconnects

It is well-known that capacitance in the metallization is becoming too great to allow the continued use of SiO/sub 2/ as the intermetal dielectric below about the 0.25 /spl mu/m technology node. One of many possible replacements for SiO/sub 2/ are organic polymers. Organic polymers are not drop-in replacements, however, and their successful integration into functional circuits requires new fabrication procedures and integration schemes. The embedded dielectric scheme offers a sound evolutionally path for their successful integration into a subtractive etch, aluminum-based integrated circuit. The embedded dielectric scheme effectively lowers total capacitance and the line-line/total capacitance ratio while minimally changing the rest of the metallization fabrication processes including via formation. Vapor deposited polymers which are conformably deposited like Parylene-n are more easily integrated into the embedded dielectric scheme than nonconformal spin-on dielectric films. Parylene-n copolymers with dielectric permittivities as low as 2.3 also are excellent candidate materials for use in the embedded dielectric scheme and they also have equivalent thermal stability as the homopolymer. New copolymers with comonomers of different functionality should improve both the adhesion and thermal stability of the intermetal dielectric.