Odysseas G. Koufopavlou

Architectures and VLSI implementations of the AES-Proposal Rijndael

Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decryption process. They reduce the required hardware resources and achieve high-speed performance. Their design philosophy is completely different. The first uses feedback logic and reaches a throughput value equal to 259 Mbit/sec. It performs efficiently in applications with low covered area resources. The second architecture is optimized for high-speed performance using pipelined technique. Its throughput can reach 3.65 Gbit/sec.

Implementation of the SHA-2 Hash Family Standard Using FPGAs

The continued growth of both wired and wireless communications has triggered the revolution for the generation of new cryptographic algorithms. SHA-2 hash family is a new standard in the widely used hash functions category. An architecture and the VLSI implementation of this standard are proposed in this work. The proposed architecture supports a multi-mode operation in the sense that it performs all the three hash functions (256, 384 and 512) of the SHA-2 standard. The proposed system is compared with the implementation of each hash function in a separate FPGA device. Comparing with previous designs, the introduced system can work in higher operation frequency and needs less silicon area resources. The achieved performance in the term of throughput of the proposed system/architecture is much higher (in a range from 277 to 417%) than the other hardware implementations. The introduced architecture also performs much better than the implementations of the existing standard SHA-1, and also offers a higher security level strength. The proposed system could be used for the implementation of integrity units, and in many other sensitive cryptographic applications, such as, digital signatures, message authentication codes and random number generators.

Hardware implementation of the RC4 stream cipher

In this paper, an efficient hardware implementation of the RC4 stream-cipher is proposed. In contrary to previous designs, which support only fixed length key, the proposed implementation integrates in the same hardware module an 8-bit up to 128-bit key length capability. Independently of the key length, the proposed VLSI implementation achieves a data throughput up to 22 Mbytes/sec in a maximum frequency of 64 MHz. The whole design was captured by using VHDL language and a FPGA device was used for the hardware implementation of the architecture. A detailed analysis, in terms of performance, and covered area is shown.

On the hardware implementations of the SHA-2 (256, 384, 512) hash functions

Couple to the communications wired and unwired networks growth, is the increasing demand for strong secure data transmission. New cryptographic standards are developed, and new encryption algorithms are designed, in order to satisfy the special needs for security. SHA-2 is the newest powerful standard in the hash functions families. In this paper, a VLSI architecture for the SHA-2 family is proposed. For every hash function SHA-2 (256, 384, and 512) of this standard, a hardware implementation is presented. All the implementations are examined and compared in the supported security level and in the performance by using hardware terms. This work can substitute efficiently the previous SHA-1 standard implementations, in every integrity security scheme, with higher offered security level, and better performance. In addition, the proposed implementations could be applied alternatively in the integrations of digital signature algorithms, keyed-hash message authentication codes and in random numbers generators architectures.

An efficient reconfigurable multiplier architecture for Galois field GF(2m)

This paper describes an efficient architecture of a reconfigurable bit-serial polynomial basis multiplier for Galois field GFð2 m Þ; where 1 , m # M: The value m; of the irreducible polynomial degree, can be changed and so, can be configured and programmed. The value of M determines the maximum size that the multiplier can support. The advantages of the proposed architecture are (i) the high order of flexibility, which allows an easy configuration for different field sizes, and (ii) the low hardware complexity, which results in small area. By using the gated clock technique, significant reduction of the total multiplier power consumption is achieved. q 2003 Elsevier Ltd. All rights reserved.

High speed networking security: design and implementation of two new DDP-based ciphers

Using Data-Dependent (DD) Permutations (DDP) as main cryptographic primitive two new ciphers are presented: ten-round Cobra-H64, and twelve-round Cobra-H128. The designed ciphers operate efficiently with different plaintext lengths, 64 and 128-bit, for Cobra-H64 and Cobra-H128, respectively. Both of them use very simple key scheduling that defines high performance, especially in the case of frequent key refreshing. A novel feature of Cobra-H64 and Cobra-H128 is the use of the Switchable Operations which prevent the weak keys. The offered high-level security strength does not sacrifice the implementation performance, of both ciphers. Architecture, design and hardware implementation of the two ciphers are presented. The synthesis results for both FPGA and ASIC implementations prove that Cobra-H64 and Cobra-H128 are very flexible and powerful new ciphers, especially for high-speed networks. The achieved hardware performance and the implementation area cost of Cobra-H64 and Cobra-H128 are compared with other ciphers, used in security layers of wireless protocols (Bluetooth, WAP, OMA, UMTS and IEEE 802.11). From these comparisons it is proven that the two proposed are flexible new ciphers with better performance in most of the cases, suitable for wireless communications networks of present and future.

Comparison of the hardware architectures and FPGA implementations of stream ciphers

In this paper, the hardware implementations of five representative stream ciphers are compared in terms of performance and consumed area. The ciphers used for the comparison are the A5/1, W7, E0, RC4 and Helix. The first three ones have been used for the security part of well-known standards. The Helix cipher is a recently introduced fast, word oriented, stream cipher. The W7 algorithm has been recently proposed as a more trustworthy solution for GSM, due to the security problems that occurred concerning the A5/1 strength. The designs were coded using the VHDL language. For the hardware implementation of the designs, an FPGA device was used. The implementation results illustrate the hardware performance of each cipher in terms of throughput-to-area ratio. This ratio equals: 5.88 for the A5/1, 1.26 for the W7, 0.21 for the E0, 2.45 for the Helix and 0.86 for the RC4.

VLSI implementation of the keyed-hash message authentication code for the wireless application protocol

Security has become a highly critical issue in the provision of mobile services. The Wireless Application Protocol (WAP) has specified a powerful security layer, the WTLS. The Keyed-Hash Authentication Code (HMAC) has been adopted by the WTLS in order to support the special demands for authentication with security of high-level strength. A VLSI architecture and the FPGA implementation of HMAC for the WTLS are proposed in this work. The introduced design is based on the SHA-1 hash function. The implementation results for both the HMAC and the SHA-1 proposed architectures are compared with other related works. From these comparisons, it is proven that the proposed system performs better in all of the cases. It is also superior to the conventional hardware implementations by using the area-delay product. In addition to the WAP protocol, the proposed architecture can be implemented for any authentication system of computer networks and wireless protocols, with high-performance demands and hard secure authentication needs at the same time.

An ultra high speed architecture for VLSI implementation of hash functions

Today, security is a topic which attacks the great interest of researchers. Many encryption algorithms have been investigated, and developed in the last years. The research community efforts are also centered to the efficient implementation of them, in both software platforms and hardware devices. This work is related to hash functions FPGA implementation. Two different hash functions are studied: RIPEMD-160 and SHA-1. A high speed architecture is proposed for the implementation of both of them in the same hardware module. The proposed system reaches throughput values equal to 1,4 for SHA-1 and 1,6 for RIPEMND-160. The proposed system is compared with other related works in both software and hardware.

Hardware implementation of Bluetooth security

Bluetooth can implement its security layers key-generation mechanism and authentication in software or hardware. Software implementation usually satisfies user requirements, but in time-critical applications or processing-constrained devices, a hardware implementation is preferable.