Labros Bisdounis

Propagation delay and short-circuit power dissipation modeling of the CMOS inverter

This paper introduces a new, accurate analytical model for the evaluation of the delay and the short-circuit power dissipation of the CMOS inverter. Following a detailed analysis of the inverter operation, accurate expressions for the output response to an input ramp are derived. Based on this analysis improved analytical formulae for the calculation of the propagation delay and short-circuit power dissipation, are produced. Analytical expressions for all inverter operation regions and input waveform slopes are derived, which take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The effective output transition time of the inverter is determined in order to map the real output voltage waveform to a ramp waveform for the model to be applicable in an inverter chain. The final results are in very good agreement with SPICE simulations.

Instruction level energy modeling for pipelined processors

A new method for creating instruction level energy models for pipelined processors is introduced. This method is based on measuring the instantaneous current drawn by the processor during the execution of the instructions. An appropriate instrumentation set up was established for this purpose. According to the proposed method the energy costs (base and inter-instruction costs) are modeled in relation to a reference instruction (e.g. NOP). These costs incorporate inter-cycle energy components, which cancel each other when they are summed to produce the energy consumption of a program resulting in estimates with high accuracy. This is confirmed by the results. Also the dependencies of the energy consumption on the instruction parameters (e.g. operands, addresses) are studied and modeled in an efficient way.

A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits

An important issue in the design of VLSI circuits is the choice of the basic circuit approach and topology for implementing various logic and arithmetic functions. In this paper, several static and dynamic CMOS circuit design styles are evaluated in terms of area, propagation delay and power dissipation. The different design styles are compared by performing detailed transistor-level simulations on a benchmark circuit using HSPICE, and analysing the results in a statistical way. Based on the results of our analysis, some of the trade-offs that are possible during the design phase in order to improve the circuit power-delay product are identified.

Instrumentation Set-up for Instruction Level Power Modeling

Energy constraints form an important part of the design specification for processors running embedded applications. For estimating energy dissipation early at the design cycle, accurate power consumption models characterized for the processor are essential. A methodology and the corresponding instrumentation setup for taking current measurements to create high quality instruction level power models, are discussed in this paper. The instantaneous current drawn by the processor is monitored at each clock cycle. A high performance instrumentation setup has been established for the accurate measurement of the processor current, which is based on a current sensing circuit, instead of the conventional solution of a series resistor.

Modeling the CMOS short-circuit power dissipation

This paper presents a detailed analysis of the CMOS short-circuit power dissipation, on the basis of an elementary CMOS inverter. Accurate, analytical expressions for the inverter output response to an input ramp are derived, which result in an improved formula for the calculation of the short-circuit power dissipation. This improvement is due to the fact that the new derivations take into account the complete expression of the short-circuit current.

Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices

This paper presents an accurate model for the evaluation of the CMOS short-circuit power dissipation for short-channel devices, on the basis of a CMOS inverter. The improvement of the proposed approach against previous works is due to the new derived, accurate, analytical expressions for the inverter output waveform which include for the first time the influences of both transistor currents, and the gate-to-drain coupling capacitance. The results produced by she suggested model show good agreement with SPICE simulations.

Modeling the dynamic behavior of series-connected MOSFETs for delay analysis of multiple-input CMOS gates

In this paper the dynamic behavior of series-connected MOSFETs is studied, in order to compute the propagation delay of multiple-input static CMOS gates. A method for the reduction of series-connected MOSFETs to a simple MOSFET with the same behavior is proposed. The effective width of the equivalent transistor is not constant as in some previous works. So all cases of input slopes, the load capacitance, the number and the position of the switching inputs, and the body effect, are considered in order to determine the equivalent transistors width. Along with the reduction process, an accurate analytical inverter timing model is used to compute the propagation delay of multiple-input static gates. The produced results are in very good agreement with SPICE simulations.

Switching response modeling of the CMOS inverter for sub-micron devices

In this paper an accurate, analytical model for the evaluation of the CMOS inverter delay in the sub-micron regime, is presented. A detailed analysis of the inverter operation is provided which results in accurate expressions describing the output waveform. These analytical expressions are valid for all the inverter operation regions and input waveform slopes. They take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The presented model shows clearly the influence of the inverter design characteristics, the load capacitance, and the slope of the input waveform driving the inverter on the propagation delay. The results are in excellent agreement with SPICE simulations.

A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design

We present the design exploration of a system-on-chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of an ad-hoc C++ simulation environment, integrating power models for CPUs, memories and buses used in the design and incorporating software profiling capabilities. The architecture is based on two ARM microprocessors, an AMBA bus and a local bus, DMA unit and other peripherals. Software mapping on the processor has been based on the power/performance profiling results.

A Multi-level Validation Methodology for Wireless Network Applications *

This paper presents the validation methodology established and ap-plied during the development of a wireless LAN application. The target of the development is the implementation of the hardware physical layer of the HIPERLAN/2 wireless LAN protocol and its interface with the upper layers. The implementation of the physical layer (modem) has been validated in two different levels. First, at the functional level, the modem was validated by a high-level UML model. Then, at the implementation level, a new validation framework drives the validation procedure at three different sub-levels of de-sign abstraction (numerical representation, VHDL coding, FPGA-based proto-typing). Using this validation methodology, the prototype of the HIPERLAN/2 modem has been designed and validated successfully.